Datasheet

 2010 Microchip Technology Inc. Preliminary DS39974A-page 541
PIC18F47J13 FAMILY
APPENDIX A: REVISION HISTORY
Revision A (March 2010)
Original data sheet for PIC18F47J13 family devices.
APPENDIX B: MIGRATION FROM
PIC18F46J11 TO
PIC18F47J13
Code for the devices in the PIC18F46J11 family can be
migrated to the PIC18F47J13 without many changes.
The differences between the two device families are
listed in Table B-1.
TABLE B-1: NOTABLE DIFFERENCES BETWEEN PIC18F47J13 AND PIC18F46J11 FAMILIES
Characteristic PIC18F47J13 Family 18F46J11 Family
Maximum Program Memory 128 Kbytes 64 Kbytes
Oscillator Options PLL can be enabled at start-up with the
Configuration bit option.
96 MHz PLL circuit is available via the
Configuration bit setting, allowing
48 MHz operation from INTOSC.
Default 4x PLL circuit is still available.
Requires firmware to set the PLLEN bit
at run time.
4x PLL circuit only. Maximum operating
frequency from INTOSC is 32 MHz.
SOSC Oscillator Options Low-power oscillator option for SOSC,
with run-time switch.
Low-power oscillator option for SOSC,
only via the Configuration bit setting.
T1CKI Clock Input T1CKI can be used as a clock input
without enabling the Timer1 oscillator.
No
Timers 8 5
ECCP 3 2
CCP 7 0
SPI F
OSC/8 Master Clock
Option
Yes No
Second I
2
C™ Port Yes, all packages. Yes, but only on 44-pin devices.
ADC 13 Channel, 10/12-Bit Conversion modes
with Special Event Trigger option.
13 Channel, 10-bit only.
Peripheral Module Disable
Bits
Yes, allowing further power reduction. No
Band Gap Voltage Reference
Output
Yes, enabled on pin, RA1, by setting the
VBGOE bit (WDTCON<4>).
No
REPU/RDPU Pull-Up Enable
Bits
Moved to TRISE register (avoids read,
modify, write issues).
Pull-up bits configured in PORTE register
Comparators Three, each with four input pin selections. Two, each with two input pin selections.
Increased Output Drive
Strength
RA0 through RA5, RDx and REx. No
PWRT Period F Devices – 500
s
LF Devices – 46 ms
F Devices – 1 ms
LF Devices – 64 ms