Datasheet

 2010 Microchip Technology Inc. Preliminary DS39974A-page 377
PIC18F47J13 FAMILY
FIGURE 22-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
FIGURE 22-4: A/D CONVERSION T
AD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
22.7 A/D Converter Calibration
The A/D Converter in the PIC18F47J13 family of
devices includes a self-calibration feature, which com-
pensates for any offset generated within the module.
The calibration process is automated and is initiated by
setting the ADCAL bit (ADCON1<6>). The next time
the GO/DONE
bit is set, the module will perform an off-
set calibration and store the result internally. Thus,
subsequent offsets will be compensated.
Example 22-1 provides an example of a calibration
routine.
The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset or if there are other major changes in
operating conditions.
TAD1
TAD2
TAD3 TAD4
TAD5
TAD6 TAD7
TAD8 TAD11
Set GO/DONE bit
Holding capacitor is disconnected from analog input (typically 100 ns)
TAD9 TAD10TCY - TAD
Next Q4: ADRESH/ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion starts
b0
b9
b6
b5
b4
b3
b2
b1
b8
b7
1
2
3
4 5
6 7
8 11
Set GO/DONE bit
(Holding capacitor is disconnected)
9 10
Next Q4: ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.
Conversion starts
1
2
3
4
(Holding capacitor continues
acquiring input)
T
ACQT Cycles
TAD Cycles
Automatic
Acquisition
Time
b0b9
b6
b5 b4
b3
b2
b1
b8
b7