Datasheet

PIC18F47J13 FAMILY
DS39974A-page 36 Preliminary  2010 Microchip Technology Inc.
FIGURE 3-1: PIC18F47J13 FAMILY CLOCK DIAGRAM
OSC1
OSC2
Primary Oscillator
CPU
Peripherals
IDLE
INTOSC Postscaler
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
250 kHz
111
110
101
100
011
010
001
000
31 kHz
INTRC
31 kHz
Internal
Oscillator
Block
8 MHz
8 MHz
0
1
OSCTUNE<7>
PLLDIV<2:0>
4 MHz
WDT, PWRT, FSCM
and Two-Speed Start-up
OSCCON<6:4>
PLLEN
1
0
FOSC<2>
1
0
PLL Prescaler
96 MHz
PLL
(1)
 2
00
FOSC<2:1>
Other
00
01
OSCCON<1:0>
11
 4
RA6
CLKO
Enabled Modes
Timer1 Clock
(3)
Postscaled
Internal Clock
T1OSI
T1OSO
Secondary Oscillator
Note 1: The 96 MHz PLL requires a 4 MHz input and it produces a 96 MHz output. The 96 MHz PLL prescaler enables
source clocks of 4, 8, 12, 16, 20, 24, 40 or 48 MHz to provide the 4 MHz input.
2: The 4x PLL requires an input clock source between 4 and 12 MHz. When using INTOSC to provide the 4x PLL
input, the INTOSC postscaler must be set to either 8 MHz or 4 MHz. Selecting other INTOSC postscaler settings
will operate the PLL outside of the specification.
3: Selecting the Timer1 clock or postscaled internal clock will turn off the primary oscillator (unless required by the
reference clock of Section 3.4 “Reference Clock Output”) and PLL.
 12
 10
 6
 5
 4
 3
 2
 1
000
001
010
011
100
101
110
111
48 MHz
Primary Clock
Source
CFGPLLEN
1
0
0
1
4x PLL
(2)
PLLSEL
FOSC<2>