Datasheet

PIC18F47J13 FAMILY
DS39974A-page 322 Preliminary  2010 Microchip Technology Inc.
FIGURE 20-11: I
2
C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001
(RECEPTION, 10-BIT ADDRESS)
(1,2)
SDAx SCLx SSPxIF (PIR1<3> or PIR3<7>) BF (SSPxSTAT<0>)
S
123456789 123456789 12345 789
P
1 1 1 1 0 A9 A8 A7 A6 A5 X A3 A2 X X D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
D2
6
Cleared in software
Receive Second Byte of Address
Cleared by hardware when SSPxADD is updated with low byte of address
UA (SSPxSTAT<1>)
Clock is held low until update of SSPxADD has taken place
UA is set indicating that the SSPxADD needs to be updated
UA is set indicating that SSPxADD needs to be updated
Cleared by hardware when SSPxADD is updated with high byte of address
SSPxBUF is written with contents of SSPxSR
Dummy read of SSPxBUF to clear BF flag
ACK
CKP (SSPxCON1<4>)
12345 789
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master terminates transfer
D2
6
ACK
Cleared in software
Cleared in software
SSPOV (SSPxCON1<6>)
SSPOV is set because SSPxBUF is still full. ACK is not sent.
(CKP does not reset to ‘0’ when SEN = 0)
Clock is held low until update of SSPxADD has taken place
Note 1: In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X.X will be Acknowledged and cause an interrupt.
2: Note that the Most Significant bits of the address are not affected by the bit masking.