Datasheet

2010 Microchip Technology Inc. Preliminary DS39974A-page 289
PIC18F47J13 FAMILY
19.4.8 OPERATION IN POWER-MANAGED
MODES
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the ECCPx pin is driving a value, it will con-
tinue to drive that value. When the device wakes up, it
will continue from this state. If Two-Speed Start-ups are
enabled, the initial start-up frequency from HFINTOSC
and the postscaler may not be immediately stable.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCPx module without change.
19.4.8.1 Operation with Fail-Safe
Clock Monitor (FSCM)
If the Fail-Safe Clock Monitor (FSCM) is enabled, a clock
failure will force the device into the power-managed
RC_RUN mode and the OSCFIF bit of the PIR2 register
will be set. The ECCPx will then be clocked from the
internal oscillator clock source, which may have a
different clock frequency than the primary clock.
19.4.9 EFFECTS OF A RESET
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the ECCP registers to their
Reset states.
This forces the ECCP module to reset to a state
compatible with previous, non-enhanced CCP modules
used on other PIC18 and PIC16 devices.
TABLE 19-4: REGISTERS ASSOCIATED WITH ECCP1/2/3 MODULE AND
TIMER1/2/3/4/6/8
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
RCON IPEN CM RI TO PD POR BOR
PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
PIR2
OSCFIF CM2IF CM1IF BCL1IF HLVDIF TMR3IF CCP2IF
PIR4 CCP10IF CCP9IF CCP8IF CCP7IF CCP6IF CCP5IF CCP4IF CCP3IF
PIE1
PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
PIE2
OSCFIE CM2IE CM1IE BCL1IE HLVDIE TMR3IE CCP2IE
PIE4 CCP10IE CCP9IE CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE
IPR1
PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
IPR2
OSCFIP CM2IP CM1IP BCL1IP HLVDIP TMR3IP CCP2IP
IPR4 CCP10IP CCP9IP CCP8IP CCP7IP CCP6IP CCP5IP CCP4IP CCP3IP
TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
TRISC TRISC7 TRISC6
TRISC2 TRISC1 TRISC0
TRISE RDPU REPU TRISE2 TRISE1 TRISE0
TMR1H Timer1 Register High Byte
TMR1L Timer1 Register Low Byte
TMR2 Timer2 Register
TMR3H Timer3 Register High Byte
TMR3L Timer3 Register Low Byte
TMR4 Timer4 Register
TMR6 Timer6 Register
TMR8 Timer8 Register
PR2 Timer2 Period Register
PR4 Timer4 Period Register
PR6 Timer6 Period Register
PR8 Timer8 Period Register
T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
RD16 TMR1ON
T2CON
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 T3OSCEN T3SYNC
RD16 TMR3ON
T4CON
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0
T6CON
T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0