Datasheet

 2010 Microchip Technology Inc. Preliminary DS39974A-page 163
PIC18F47J13 FAMILY
10.7.6 PERIPHERAL PIN SELECT
REGISTERS
The PIC18F47J13 family of devices implements a total
of 37 registers for remappable peripheral configuration
of 44-pin devices. The 28-pin devices have 31 registers
for remappable peripheral configuration.
Note: Input and output register values can only be
changed if IOLOCK (PPSCON<0>) = 0.
See Example 10-7 for a specific command
sequence.
REGISTER 10-5: PPSCON: PERIPHERAL PIN SELECT INPUT REGISTER 0 (BANKED EBFh)
(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — —IOLOCK
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 Unimplemented: Read as ‘0’
bit 0 IOLOCK: I/O Lock Enable bit
1 = I/O lock is active, RPORx and RPINRx registers are write-protected
0 = I/O lock is not active, pin configurations can be changed
Note 1: Register values can only be changed if IOLOCK (PPSCON<0>) = 0.
REGISTER 10-6: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 (BANKED EE1h)
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — — INTR1R4 INTR1R3 INTR1R2 INTR1R1 INTR1R0
bit 7 bit 0
Legend: R/W
= Readable bit, Writable bit if IOLOCK = 0
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 INTR1R<4:0>: Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bits
REGISTER 10-7: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 (BANKED EE2h)
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — — INTR2R4 INTR2R3 INTR2R2 INTR2R1 INTR2R0
bit 7 bit 0
Legend: R/W
= Readable bit, Writable bit if IOLOCK = 0
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 INTR2R<4:0>: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits