Datasheet

 2010 Microchip Technology Inc. Preliminary DS39974A-page 135
PIC18F47J13 FAMILY
REGISTER 9-16: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 (ACCESS FA5h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit
1 =High priority
0 = Low priority
bit 6 BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module)
1 =High priority
0 = Low priority
bit 5 RC2IP: EUSART2 Receive Interrupt Priority bit
1 =High priority
0 = Low priority
bit 4 TX2IP: EUSART2 Transmit Interrupt Priority bit
1 =High priority
0 = Low priority
bit 3 TMR4IE: TMR4 to PR4 Interrupt Priority bit
1 =High priority
0 = Low priority
bit 2 CTMUIP: Charge Time Measurement Unit (CTMU) Interrupt Priority bit
1 =High priority
0 = Low priority
bit 1 TMR3GIP: Timer3 Gate Interrupt Priority bit
1 =High priority
0 = Low priority
bit 0 RTCCIP: RTCC Interrupt Priority bit
1 =High priority
0 = Low priority