Datasheet

PIC18F66K80 FAMILY
DS39977F-page 86  2010-2012 Microchip Technology Inc.
FIGURE 5-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PLL TIME-OUT
TPLL
Note: TOST = 1024 clock cycles.
T
PLL  2 ms max. First three stages of the PWRT timer.