Datasheet

PIC18F66K80 FAMILY
DS39977F-page 78  2010-2012 Microchip Technology Inc.
TABLE 4-4: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Power-Managed
Mode
Clock Source
(5)
Exit Delay
Clock Ready
Status Bits
PRI_IDLE mode
LP, XT, HS
TCSD
(1)
OSTSHSPLL
EC, RC
HF-INTOSC
(2)
HFIOFS
MF-INTOSC
(2)
MFIOFS
LF-INTOSC None
SEC_IDLE mode SOSC T
CSD
(1)
SOSCRUN
RC_IDLE mode
HF-INTOSC
(2)
TCSD
(1)
HFIOFS
MF-INTOSC
(2)
MFIOFS
LF-INTOSC None
Sleep mode
LP, XT, HS T
OST
(3)
OSTSHSPLL TOST + t
rc
(3)
EC, RC TCSD
(1)
HF-INTOSC
(2)
TIOBST
(4)
HFIOFS
MF-INTOSC
(2)
MFIOFS
LF-INTOSC None
Note 1: TCSD (Parameter 38, Tab le 3 1- 11 ) is a required delay when waking from Sleep and all Idle modes, and
runs concurrently with any other required delays (see
Section 4.4 “Idle Modes”).
2: Includes postscaler derived frequencies. On Reset, INTOSC defaults to HF-INTOSC at 8 MHz.
3: TOST is the Oscillator Start-up Timer (Parameter 32, Tabl e 31 -11 ). TRC is the PLL Lock-out Timer
(Parameter F12, Table 31-7); it is also designated as T
PLL.
4: Execution continues during TIOBST (Parameter 39, Table 31-11), the INTOSC stabilization period.
5: The clock source is dependent upon the settings of the SCSx (OSCCON<1:0>), IRCFx (OSCCON<6:4>)
and FOSCx (CONFIG1H<3:0>) bits.