Datasheet

 2010-2012 Microchip Technology Inc. DS39977F-page 73
PIC18F66K80 FAMILY
REGISTER 4-1: PMD2: PERIPHERAL MODULE DISABLE REGISTER 2
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — —MODMD
(1)
ECANMD CMP2MD CMP1MD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Read as ‘0’
bit 3 MODMD: Modulator Output Module Disable bit
(1)
1 = The modulator output module is disabled; all Modulator Output registers are held in Reset and are
not writable
0 = The modulator output module is enabled
bit 2 ECANMD: Enhanced CAN Module Disable bit
1 = The Enhanced CAN module is disabled; all Enhanced CAN registers are held in Reset and are
not writable
0 = The Enhanced CAN module is enabled
bit 1 CMP2MD: Comparator 2 Module Disable bit
1 = The Comparator 2 module is disabled; all Comparator 2 registers are held in Reset and are not
writable
0 = The Comparator 2 module is enabled
bit 0 CMP1MD: Comparator 1 Module Disable bit
1 = The Comparator 1 module is disabled; all Comparator 1 registers are held in Reset and are not
writable
0 = The Comparator 1 module is enabled
Note 1: This bit is only implemented on devices with 64 pins (PIC18F6XK80, PIC18LF6XK80).