Datasheet

 2010-2012 Microchip Technology Inc. DS39977F-page 69
PIC18F66K80 FAMILY
FIGURE 4-3: TRANSITION TIMING TO RC_RUN MODE
FIGURE 4-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q4Q3Q2
OSC1
Peripheral
Program
Q1
LF-INTOSC
Q1
Counter
Clock
CPU
Clock
PC + 2PC
123 n-1n
Clock Transition
(1)
Q4Q3Q2 Q1 Q3Q2
PC + 4
Note 1: Clock transition typically occurs within 2-4 T
OSC.
Q1
Q3 Q4
OSC1
Peripheral
Program
PC
INTOSC
PLL Clock
Q1
PC + 4
Q2
Output
Q3
Q4
Q1
CPU Clock
PC + 2
Clock
Counter
Q2
Q2
Q3
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 T
OSC.
SCS<1:0> Bits Changed
TPLL
(1)
12 n-1n
Clock
OSTS Bit Set
Transition
(2)
Multiplexer
TOST
(1)