Datasheet

PIC18F66K80 FAMILY
DS39977F-page 68  2010-2012 Microchip Technology Inc.
If the IRCFx bits and the INTSRC bit are all clear, the
INTOSC output (HF-INTOSC/MF-INTOSC) is not
enabled and the HFIOFS and MFIOFS bits will remain
clear. There will be no indication of the current clock
source. The LF-INTOSC source is providing the device
clocks.
If the IRCFx bits are changed from all clear (thus,
enabling the INTOSC output) or if INTSRC or
MFIOSEL is set, the HFIOFS or MFIOFS bit is set after
the INTOSC output becomes stable. For details, see
Table 4-3.
TABLE 4-3: INTERNAL OSCILLATOR FREQUENCY STABILITY BITS
Clocks to the device continue while the INTOSC source
stabilizes after an interval of T
IOBST (Parameter 39,
Table 31-11).
If the IRCFx bits were previously at a non-zero value,
or if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the HFIOFS or
MFIOFS bit will remain set.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 4-4). When the clock
switch is complete, the HFIOFS or MFIOFS bit is
cleared, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCSx bits
are not affected by the switch. The LF-INTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor (FSCM) is enabled.
IRCF<2:0> INTSRC MFIOSEL Status of MFIOFS or HFIOFS when INTOSC is Stable
000 0 x MFIOFS = 0, HFIOFS = 0 and clock source is LF-INTOSC
000 1 0 MFIOFS = 0, HFIOFS = 1 and clock source is HF-INTOSC
000 1 1 MFIOFS = 1, HFIOFS = 0 and clock source is MF-INTOSC
Non-Zero x0MFIOFS = 0, HFIOFS = 1 and clock source is HF-INTOSC
Non-Zero x1MFIOFS = 1, HFIOFS = 0 and clock source is MF-INTOSC