Datasheet

PIC18F66K80 FAMILY
DS39977F-page 616  2010-2012 Microchip Technology Inc.
V
DD), Case 1.......................................................85
Time-out Sequence on Power-up (MCLR
Not Tied to
V
DD), Case 2.......................................................85
Time-out Sequence on Power-up (MCLR
Tied to VDD,
V
DD Rise Tpwrt)..................................................84
Timer0 and Timer1 External Clock ........................... 568
Timer1 Gate Count Enable Mode ............................. 217
Timer1 Gate Single Pulse Mode ............................... 219
Timer1 Gate Single Pulse/Toggle Combined Mode.. 220
Timer1 Gate Toggle Mode ........................................ 218
Timer3 Gate Count Enable Mode ............................. 228
Timer3 Gate Single Pulse Mode ............................... 230
Timer3 Gate Single Pulse/Toggle Combined Mode.. 231
Timer3 Gate Toggle Mode ........................................ 229
Transition for Entry to Idle Mode................................. 71
Transition for Entry to SEC_RUN Mode ..................... 67
Transition for Entry to Sleep Mode ............................. 70
Transition for Two-Speed Start-up (INTOSC to HSPLL).
476
Transition for Wake from Idle to Run Mode ................ 71
Transition for Wake from Sleep (HSPLL).................... 70
Transition from RC_RUN Mode to PRI_RUN Mode ... 69
Transition from SEC_RUN Mode to PRI_RUN Mode
(HSPLL) .............................................................. 67
Transition to RC_RUN Mode ......................................69
Timing Diagrams and Specifications
Capture/Compare/PWM Requirements .................... 569
CLKO and I/O Requirements ............................ 564, 565
EUSART/AUSART Synchronous Receive Requirements
578
EUSART/AUSART Synchronous Transmission Require-
ments ................................................................ 578
Example SPI Mode Requirements (Master Mode, CKE =
0).......................................................................570
Example SPI Mode Requirements (Master Mode, CKE =
1).......................................................................571
Example SPI Mode Requirements (Slave Mode, CKE =
0).......................................................................572
Example SPI Slave Mode Requirements (CKE = 1) . 573
External Clock Requirements ................................... 562
HLVD Characteristics................................................ 567
I
2
C Bus Data Requirements (Slave Mode) ............... 575
I
2
C Bus Start/Stop Bits Requirements (Slave Mode) 574
Internal RC Accuracy (INTOSC) ............................... 563
MSSP I
2
C Bus Data Requirements .......................... 577
MSSP I
2
C Bus Start/Stop Bits Requirements ........... 576
PLL Clock.................................................................. 563
Reset, Watchdog Timer, Oscillator Start-up Timer, Pow-
er-up Timer and Brown-out Reset Requirements ...
566
Timer0 and Timer1 External Clock Requirements .... 568
Top-of-Stack Access......................................................... 103
TSTFSZ............................................................................. 523
Two-Speed Start-up .................................................. 457, 476
IESO (CONFIG1H, Internal/External Oscillator Switcho-
ver Bit................................................................ 460
Two-Word Instructions
Example Cases......................................................... 107
TXSTAx Register
BRGH Bit .................................................................. 337
U
Ultra Low-Power Mode
Regulators
Enable Mode..................................................... 474
Operation in Sleep ............................................ 475
Ultra Low-Power Wake-up
Exit Delay ................................................................... 78
Overview..................................................................... 77
V
Voltage Reference Specifications..................................... 559
W
Watchdog Timer (WDT)............................................ 457, 472
Associated Registers................................................ 473
Control Register........................................................ 473
During Oscillator Failure ........................................... 477
Programming Considerations ................................... 472
WCOL ....................................................... 320, 321, 322, 325
WCOL Status Flag.................................... 320, 321, 322, 325
WWW Address ................................................................. 617
WWW, On-Line Support ....................................................... 9
X
XORLW............................................................................. 523
XORWF ............................................................................ 524