Datasheet

 2010-2012 Microchip Technology Inc. DS39977F-page 615
PIC18F66K80 FAMILY
TMR1H Register ....................................................... 209
TMR1L Register........................................................ 209
Timer2............................................................................... 221
Associated Registers ................................................ 222
Interrupt..................................................................... 222
Operation .................................................................. 221
Output ....................................................................... 222
PR2 Register............................................................. 262
TMR2 to PR2 Match Interrupt................................... 262
Timer3............................................................................... 223
16-Bit Read/Write Mode............................................ 227
Associated Registers ................................................ 232
Gates ........................................................................ 228
Operation .................................................................. 226
Oscillator ................................................................... 223
Overflow Interrupt ............................................. 223, 232
SOSC Oscillator
Use as the Timer3 Clock Source ...................... 227
Special Event Trigger (ECCP) .................................. 232
TMR3H Register ....................................................... 223
TMR3L Register........................................................ 223
Timer4............................................................................... 233
Associated Registers ................................................ 234
Interrupt..................................................................... 234
Operation .................................................................. 233
Output ....................................................................... 234
Postscaler.
See Postscaler, Timer4.
PR4 Register............................................................. 233
Prescaler.
See Prescaler, Timer4.
TMR4 Register.......................................................... 233
Timing Diagrams
A/D Conversion......................................................... 580
Asynchronous Reception .......................................... 347
Asynchronous Transmission..................................... 344
Asynchronous Transmission (Back-to-Back) ............ 344
Automatic Baud Rate Calculation ............................. 342
Auto-Wake-up Bit (WUE) During Normal Operation . 349
Auto-Wake-up Bit (WUE) During Sleep .................... 349
Baud Rate Generator with Clock Arbitration ............. 319
BRG Overflow Sequence.......................................... 342
BRG Reset Due to SDA Arbitration During Start Condi-
tion .................................................................... 328
Brown-out Reset (BOR)............................................ 566
Bus Collision During a Repeated Start Condition (Case
1)....................................................................... 329
Bus Collision During a Repeated Start Condition (Case
2)....................................................................... 329
Bus Collision During a Start Condition (SCL = 0) ..... 328
Bus Collision During a Stop Condition (Case 1) ....... 330
Bus Collision During a Stop Condition (Case 2) ....... 330
Bus Collision During Start Condition (SDA Only)...... 327
Bus Collision for Transmit and Acknowledge............ 326
Capture/Compare/PWM (ECCP1, ECCP2) .............. 569
CLKO and I/O ........................................................... 564
Clock/Instruction Cycle ............................................. 106
DSM Carrier High Synchronization (MDCHSYNC = 1,
MDCLSYNC = 0) .............................................. 198
DSM Carrier Low Synchronization (MDCHSYNC = 0,
MDCLSYNC = 1) .............................................. 199
DSM Full Synchronization (MDCHSYNC = 1, MD-
CLSYNC = 1).................................................... 199
DSM No Synchronization (MDCHSYNC = 0, MD-
CLSYNC = 0).................................................... 198
DSM On-Off Keying (OOK) Synchronization ............ 198
Enhanced PWM Output (Active-High) ...................... 272
Enhanced PWM Output (Active-Low) ....................... 273
EUSART Synchronous Transmission (Master/Slave) ....
578
EUSART/AUSART Synchronous Receive (Master/
Slave) ............................................................... 578
Example SPI Master Mode (CKE = 0)...................... 570
Example SPI Master Mode (CKE = 1)...................... 571
Example SPI Slave Mode (CKE = 0)........................ 572
Example SPI Slave Mode (CKE = 1)........................ 573
External Clock .......................................................... 562
Fail-Safe Clock Monitor (FSCM)............................... 478
First Start Bit Timing ................................................. 320
Full-Bridge PWM Output........................................... 276
Half-Bridge PWM Output .................................. 274, 281
High-Voltage Detect Operation (VDIRMAG = 1) ...... 389
HLVD Characteristics ............................................... 567
I
2
C Acknowledge Sequence..................................... 325
I
2
C Bus Data............................................................. 575
I
2
C Bus Start/Stop Bits ............................................. 574
I
2
C Master Mode (7 or 10-Bit Transmission) ............ 323
I
2
C Master Mode (7-Bit Reception) .......................... 324
I
2
C Slave Mode (10-Bit Reception, SEN = 0, ADMSK =
01001) .............................................................. 308
I
2
C Slave Mode (10-Bit Reception, SEN = 0)........... 309
I
2
C Slave Mode (10-Bit Reception, SEN = 1)........... 314
I
2
C Slave Mode (10-Bit Transmission) ..................... 310
I
2
C Slave Mode (7-bit Reception, SEN = 0, ADMSK =
01011) .............................................................. 306
I
2
C Slave Mode (7-Bit Reception, SEN = 0)............. 305
I
2
C Slave Mode (7-Bit Reception, SEN = 1)............. 313
I
2
C Slave Mode (7-Bit Transmission) ....................... 307
I
2
C Slave Mode General Call Address Sequence (7 or
10-Bit Addressing Mode) .................................. 315
I
2
C Stop Condition Receive or Transmit Mode......... 325
Low-Voltage Detect Operation (VDIRMAG = 0) ....... 388
MSSP Clock Synchronization................................... 312
MSSP I
2
C Bus Data ................................................. 576
MSSP I
2
C Bus Start/Stop Bits.................................. 576
Parallel Slave Port (PSP) Read................................ 194
Parallel Slave Port (PSP) Write ................................ 193
PWM Auto-Shutdown with Auto-Restart Enabled .... 280
PWM Auto-Shutdown with Firmware Restart ........... 280
PWM Direction Change ............................................ 277
PWM Direction Change at Near 100% Duty Cycle... 278
PWM Output ............................................................. 262
Repeated Start Condition ......................................... 321
Reset, Watchdog Timer (WDT), Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) ................ 565
Send Break Character Sequence............................. 350
Slave Synchronization .............................................. 293
Slow Rise Time (MCLR
Tied to VDD, VDD Rise > TPWRT)
85
SPI Mode (Master Mode) ......................................... 292
SPI Mode (Slave Mode, CKE = 0)............................ 294
SPI Mode (Slave Mode, CKE = 1)............................ 294
Steering Event at Beginning of Instruction (STRSYNC =
1) ...................................................................... 284
Steering Event at End of Instruction (STRSYNC = 0) ....
284
Synchronous Reception (Master Mode, SREN) ....... 353
Synchronous Transmission ...................................... 351
Synchronous Transmission (Through TXEN) ........... 352
Time-out Sequence on POR w/ PLL Enabled (MCLR
Tied to VDD)........................................................ 86
Time-out Sequence on Power-up (MCLR
Not Tied to