Datasheet

PIC18F66K80 FAMILY
DS39977F-page 614  2010-2012 Microchip Technology Inc.
SLRCON (Slew Rate Control)................................... 174
SSPCON1 (MSSP Control 1, I
2
C Mode) .................. 298
SSPCON1 (MSSP Control 1, SPI Mode).................. 289
SSPCON2 (MSSP Control 2, I
2
C Master Mode) ...... 299
SSPCON2 (MSSP Control 2, I
2
C Slave Mode) ........ 300
SSPMSK (I
2
C Slave Address Mask).........................300
SSPSTAT (MSSP Status, I
2
C Mode)........................ 297
SSPSTAT (MSSP Status, SPI Mode) ....................... 288
STATUS....................................................................122
STKPTR (Stack Pointer) ........................................... 104
T0CON (Timer0 Control)........................................... 205
T1CON (Timer1 Control)........................................... 209
T1GCON (Timer1 Gate Control) ............................... 211
T2CON (Timer2 Control)........................................... 221
T3CON (Timer3 Control)........................................... 223
T3GCON (Timer3 Gate Control) ............................... 224
T4CON (Timer4 Control)........................................... 233
TXBIE (Transmit Buffers Interrupt Enable) ............... 437
TXBnCON (Transmit Buffer n Control) ..................... 400
TXBnDLC (Transmit Buffer n Data Length Code)..... 403
TXBnDm (Transmit Buffer n Data Field Byte m)....... 402
TXBnEIDH (Transmit Buffer n Extended Identifier, High
Byte).................................................................. 401
TXBnEIDL (Transmit Buffer n Extended Identifier, Low
Byte).................................................................. 402
TXBnSIDH (Transmit Buffer n Standard Identifier, High
Byte).................................................................. 401
TXBnSIDL (Transmit Buffer n Standard Identifier, Low
Byte).................................................................. 401
TXERRCNT (Transmit Error Count).......................... 403
TXSTAx (Transmit Status and Control) .................... 334
WDTCON (Watchdog Timer Control)........................ 473
WPUB (Weak Pull-up PORTB Enable)..................... 172
RESET .............................................................................. 513
Resets ......................................................................... 79, 457
Brown-out Reset (BOR) ............................................ 457
Oscillator Start-up Timer (OST) ................................ 457
Power-on Reset (POR) ............................................. 457
Power-up Timer (PWRT) .......................................... 457
RETFIE ............................................................................. 514
RETLW.............................................................................. 514
RETURN ........................................................................... 515
Return Address Stack ....................................................... 103
Return Stack Pointer (STKPTR) ....................................... 104
Revision History ................................................................ 601
RLCF................................................................................. 515
RLNCF ..............................................................................516
RRCF ................................................................................ 516
RRNCF.............................................................................. 517
S
SCK................................................................................... 287
SDI ....................................................................................287
SDO ..................................................................................287
SEC_IDLE Mode.................................................................71
SEC_RUN Mode ................................................................. 66
Selective Peripheral Module Control................................... 72
Serial Clock, SCK..............................................................287
Serial Data In (SDI) ........................................................... 287
Serial Data Out (SDO) ...................................................... 287
Serial Peripheral Interface.
See SPI Mode.
SETF .................................................................................517
Shoot-Through Current ..................................................... 281
Slave Select (SS
) .............................................................. 287
SLEEP...............................................................................518
Sleep Mode ......................................................................... 70
Software Simulator (MPLAB SIM) .................................... 535
Special Event Trigger.
See Compare (CCP Module).
Special Event Trigger.
See Compare (ECCP Mode).
SPI Mode (MSSP) ............................................................ 287
Associated Registers................................................ 295
Bus Mode Compatibility ............................................ 295
Effects of a Reset ..................................................... 295
Enabling SPI I/O ....................................................... 291
Master Mode............................................................. 292
Master/Slave Connection.......................................... 291
Operation.................................................................. 290
Operation in Power-Managed Modes....................... 295
Serial Clock............................................................... 287
Serial Data In............................................................ 287
Serial Data Out ......................................................... 287
Slave Mode............................................................... 293
Slave Select.............................................................. 287
Slave Select Synchronization ................................... 293
SPI Clock.................................................................. 292
SSPBUF Register..................................................... 292
SSPSR Register ....................................................... 292
Typical Connection ................................................... 291
SS
..................................................................................... 287
SSPOV ............................................................................. 322
SSPOV Status Flag .......................................................... 322
SSPSTAT Register
R/W
Bit ............................................................. 301, 304
Stack Full/Underflow Resets............................................. 105
SUBFSR ........................................................................... 529
SUBFWB .......................................................................... 518
SUBLW ............................................................................. 519
SUBULNK......................................................................... 529
SUBWF............................................................................. 519
SUBWFB .......................................................................... 520
SWAPF ............................................................................. 520
T
Table Pointer Operations (table)....................................... 132
Table Reads/Table Writes ................................................ 105
TBLRD .............................................................................. 521
TBLWT.............................................................................. 522
Time-out in Various Situations (table)................................. 84
Timer0............................................................................... 205
Associated Registers................................................ 207
Operation.................................................................. 206
Overflow Interrupt ..................................................... 207
Prescaler .................................................................. 207
Switching Assignment ...................................... 207
Prescaler Assignment (PSA Bit)............................... 207
Prescaler Select (T0PS2:T0PS0 Bits) ...................... 207
Reads and Writes in 16-Bit Mode............................. 206
Source Edge Select (T0SE Bit) ................................ 206
Source Select (T0CS Bit).......................................... 206
Timer1............................................................................... 209
16-Bit Read/Write Mode ........................................... 214
Associated Registers................................................ 220
Clock Source Selection............................................. 212
Gate.......................................................................... 216
Interrupt .................................................................... 215
Operation.................................................................. 212
Oscillator................................................................... 209
Oscillator, as Secondary Clock................................... 56
Resetting, Using the ECCP Special Event Trigger ... 216
SOSC Oscillator........................................................ 214
Layout Considerations...................................... 215
Use as a Clock Source ..................................... 215