Datasheet

 2010-2012 Microchip Technology Inc. DS39977F-page 571
PIC18F66K80 FAMILY
FIGURE 31-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
TABLE 31-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol Characteristic Min Max Units Conditions
73 TDIV2SCH,
T
DIV2SCL
Setup Time of SDI Data Input to SCK Edge 20 — ns
73A T
B2B Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
1.5 TCY + 40 — ns
74 T
SCH2DIL,
T
SCL2DIL
Hold Time of SDI Data Input to SCK Edge 40 — ns
75 T
DOR SDO Data Output Rise Time — 25 ns
76 T
DOF SDO Data Output Fall Time — 25 ns
78 T
SCR SCK Output Rise Time (Master mode) — 25 ns
79 T
SCF SCK Output Fall Time (Master mode) — 25 ns
80 T
SCH2DOV,
T
SCL2DOV
SDO Data Output Valid after SCK Edge — 50 ns
81 T
DOV2SCH,
T
DOV2SCL
SDO Data Output Setup to SCK Edge T
CY —ns
SCK
(CKPx =
0)
SCK
(CKPx =
1)
SDO
SDI
81
74
75, 76
78
80
MSb
79
73
bit 6 - - - - - - 1
LSb In
bit 6 - - - - 1
LSb
Note: Refer to Figure 31-3 for load conditions.
MSb In