Datasheet

 2010-2012 Microchip Technology Inc. DS39977F-page 517
PIC18F66K80 FAMILY
RRNCF Rotate Right f (No Carry)
Syntax: RRNCF f {,d {,a}}
Operands: 0
 f  255
d
 [0,1]
a
 [0,1]
Operation: (f<n>)
 dest<n – 1>,
(f<0>)
 dest<7>
Status Affected: N, Z
Encoding:
0100 00da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘
0’, the result
is placed in W. If ‘d’ is ‘
1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘
0’, the Access Bank will be
selected, overriding the BSR value. If ‘a’
is ‘
1’, then the bank will be selected as
per the BSR value.
If ‘a’ is ‘
0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example 1:
RRNCF REG, 1, 0
Before Instruction
REG =
1101 0111
After Instruction
REG = 1110 1011
Example 2: RRNCF REG, 0, 0
Before Instruction
W=?
REG =
1101 0111
After Instruction
W = 1110 1011
REG = 1101 0111
register f
SETF Set f
Syntax: SETF f {,a}
Operands: 0
 f  255
a
[0,1]
Operation: FFh
 f
Status Affected: None
Encoding:
0110 100a ffff ffff
Description: The contents of the specified register
are set to FFh.
If ‘a’ is ‘
0’, the Access Bank is selected.
If ‘a’ is ‘
1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘
0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
SETF REG,1
Before Instruction
REG = 5Ah
After Instruction
REG = FFh