Datasheet
PIC18F66K80 FAMILY
DS39977F-page 516 2010-2012 Microchip Technology Inc.
RLNCF Rotate Left f (No Carry)
Syntax: RLNCF f {,d {,a}}
Operands: 0
f 255
d
[0,1]
a
[0,1]
Operation: (f<n>)
dest<n + 1>,
(f<7>)
dest<0>
Status Affected: N, Z
Encoding:
0100 01da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘
0’, the result
is placed in W. If ‘d’ is ‘
1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘
0’, the Access Bank is selected.
If ‘a’ is ‘
1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘
0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example:
RLNCF REG, 1, 0
Before Instruction
REG =
1010 1011
After Instruction
REG =
0101 0111
register f
RRCF Rotate Right f through Carry
Syntax: RRCF f {,d {,a}}
Operands: 0
f 255
d
[0,1]
a
[0,1]
Operation: (f<n>)
dest<n – 1>,
(f<0>)
C,
(C)
dest<7>
Status Affected: C, N, Z
Encoding:
0011 00da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘
0’, the result is placed in W.
If ‘d’ is ‘
1’, the result is placed back in
register ‘f’ (default).
If ‘a’ is ‘
0’, the Access Bank is selected.
If ‘a’ is ‘
1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘
0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example:
RRCF REG, 0, 0
Before Instruction
REG =
1110 0110
C=0
After Instruction
REG =
1110 0110
W
= 0111 0011
C=0
C
register f