Datasheet

 2010-2012 Microchip Technology Inc. DS39977F-page 463
PIC18F66K80 FAMILY
REGISTER 28-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
R/P-1 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1
MCLRE
— — — MSSPMSK T3CKMX
(1)
T0CKMX
(1)
CANMX
bit 7 bit 0
Legend: P = Programmable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7
MCLRE: MCLR Pin Enable bit
1 = MCLR pin is enabled; RE3 input pin is disabled
0 = RE3 input pin is enabled; MCLR is disabled
bit 6-4
Unimplemented: Read as ‘0’
bit 3
MSSPMSK: MSSP V3 7-Bit Address Masking Mode Enable bit
1 = 7-Bit Address Masking mode is enabled
0 = 5-Bit Address Masking mode is enabled
bit 2
T3CKMX: Timer3 Clock Input MUX bit
(1)
1 = Timer3 gets its clock input from the RG2/T3CKI pin on 64-pin packages
0 = Timer3 gets its clock input from the RB5/T3CKI pin on 64-pin packages
bit 1
T0CKMX: Timer0 Clock Input MUX bit
(1)
1 = Timer0 gets its clock input from the RB5/T0CKI pin on 64-pin packages
0 = Timer0 gets its clock input from the RG4/T0CKI pin on 64-pin packages
bit 0
CANMX: ECAN MUX bit
1 = CANTX and CANRX pins are located on RB2 and RB3, respectively
0 = CANTX and CANRX pins are located on RC6 and RC7, respectively (28-pin and 40/44-pin
packages) or on RE4 and RE5, respectively (64-pin package)
Note 1: These bits are implemented only on the 64-pin devices (PIC18F6XK80); maintain as ‘0’ on 28-pin, 40-pin
and 44-pin devices.