Datasheet

 2010-2012 Microchip Technology Inc. DS39977F-page 423
PIC18F66K80 FAMILY
REGISTER 27-42: RXMnSIDL: RECEIVE ACCEPTANCE MASK ‘n’ STANDARD IDENTIFIER MASK
REGISTERS, LOW BYTE [0  n  1]
R/W-x R/W-x R/W-x U-0 R/W-0 U-0 R/W-x R/W-x
SID2 SID1 SID0
— EXIDEN
(1)
—EID17EID16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
SID<2:0>: Standard Identifier Mask bits or Extended Identifier Mask bits (EID<20:18>)
bit 4
Unimplemented: Read as ‘0’
bit 3 Mode 0:
Unimplemented: Read as ‘0’
Mode 1, 2
:
EXIDEN: Extended Identifier Filter Enable Mask bit
(1)
1 = Messages selected by the EXIDEN bit in RXFnSIDL will be accepted
0 = Both standard and extended identifier messages will be accepted
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID<17:16>: Extended Identifier Mask bits
Note 1: This bit is available in Mode 1 and 2 only.
REGISTER 27-43: RXMnEIDH: RECEIVE ACCEPTANCE MASK ‘n’ EXTENDED IDENTIFIER MASK
REGISTERS, HIGH BYTE [0  n  1]
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID<15:8>: Extended Identifier Mask bits
REGISTER 27-44: RXMnEIDL: RECEIVE ACCEPTANCE MASK ‘n’ EXTENDED IDENTIFIER MASK
REGISTERS, LOW BYTE [0  n  1]
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID<7:0>: Extended Identifier Mask bits