Datasheet

PIC18F66K80 FAMILY
DS39977F-page 422  2010-2012 Microchip Technology Inc.
REGISTER 27-39: RXFnEIDH: RECEIVE ACCEPTANCE FILTER ‘n’ EXTENDED IDENTIFIER
REGISTERS, HIGH BYTE [0  n  15]
(1)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID<15:8>: Extended Identifier Filter bits
Note 1: Registers, RXF6EIDH:RXF15EIDH, are available in Mode 1 and 2 only.
REGISTER 27-40: RXFnEIDL: RECEIVE ACCEPTANCE FILTER ‘n’ EXTENDED IDENTIFIER
REGISTERS, LOW BYTE [0  n  15]
(1)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EID<7:0>: Extended Identifier Filter bits
Note 1: Registers, RXF6EIDL:RXF15EIDL, are available in Mode 1 and 2 only.
REGISTER 27-41: RXMnSIDH: RECEIVE ACCEPTANCE MASK ‘n’ STANDARD IDENTIFIER MASK
REGISTERS, HIGH BYTE [0  n  1]
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
SID<10:3>: Standard Identifier Mask bits or Extended Identifier Mask bits (EID<28:21>)