Datasheet

PIC18F66K80 FAMILY
DS39977F-page 394  2010-2012 Microchip Technology Inc.
REGISTER 27-1: CANCON: CAN CONTROL REGISTER
Mode 0
R/W-1 R/W-0 R/W-0 R/S-0 R/W-0 R/W-0 R/W-0 U-0
REQOP2 REQOP1 REQOP0 ABAT WIN2 WIN1 WIN0
—
Mode 1
R/W-1 R/W-0 R/W-0 R/S-0 U0 U-0 U-0 U-0
REQOP2 REQOP1 REQOP0 ABAT
— — — —
Mode 2
R/W-1 R/W-0 R/W-0 R/S-0 R-0 R-0 R-0 R-0
REQOP2 REQOP1 REQOP0 ABAT FP3 FP2 FP1 FP0
bit 7 bit 0
Legend: S = Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
REQOP<2:0>: Request CAN Operation Mode bits
1xx = Requests Configuration mode
011 = Requests Listen Only mode
010 = Requests Loopback mode
001 = Disabled/Sleep mode
000 = Requests Normal mode
bit 4
ABAT: Abort All Pending Transmissions bit
1 = Abort all pending transmissions (in all transmit buffers)
(1)
0 = Transmissions proceeding as normal
bit 3-1 Mode 0:
WIN<2:0>: Window Address bits
These bits select which of the CAN buffers to switch into the Access Bank area. This allows access to the
buffer registers from any data memory bank. After a frame has caused an interrupt, the ICODE<3:0> bits
can be copied to the WIN<2:0> bits to select the correct buffer. See Example 27-2 for a code example.
111 = Receive Buffer 0
110 = Receive Buffer 0
101 = Receive Buffer 1
100 = Transmit Buffer 0
011 = Transmit Buffer 1
010 = Transmit Buffer 2
001 = Receive Buffer 0
000 = Receive Buffer 0
bit 0 Mode 0:
Unimplemented: Read as ‘0’
bit 4-0 Mode 1:
Unimplemented: Read as ‘0’
Mode 2:
FP<3:0>: FIFO Read Pointer bits
These bits point to the message buffer to be read.
0000 = Receive Message Buffer 0
0001 = Receive Message Buffer 1
0010 = Receive Message Buffer 2
0011 = Receive Message Buffer 3
0100 = Receive Message Buffer 4
0101 = Receive Message Buffer 5
0110 = Receive Message Buffer 6
0111 = Receive Message Buffer 7
1000:1111 Reserved
Note 1: This bit will clear when all transmissions are aborted.