Datasheet

PIC18F66K80 FAMILY
DS39977F-page 392  2010-2012 Microchip Technology Inc.
FIGURE 27-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM
MSGREQ
TXB2
ABTF MLOA TXERR MTXBUFF MESSAGE
Message
Queue
Control
Transmit Byte Sequencer
MSGREQ
TXB1
ABTF MLOA TXERR MTXBUFF MESSAGE MSGREQ
TXB0
ABTF MLOA TXERR MTXBUFF MESSAGE
Acceptance Filters
(RXF0-RXF05)
A
c
c
e
p
t
Data Field
Identifier
Acceptance Mask
RXM1
Acceptance Filters
(RXF06-RXF15)
M
A
B
Acceptance Mask
RXM0
Rcv Byte
16 - 4 to 1 MUXs
PROTOCOL
MESSAGE
BUFFERS
Transmit Option
MODE 0
MODE 1, 2
6 TX/RX
Buffers
2 RX
Buffers
CRC<14:0>
Comparator
Receive<8:0>Transmit<7:0>
Receive
Error
Transmit
Error
Protocol
REC
TEC
Err-Pas
Bus-Off
Finite
State
Machine
Counter
Counter
Shift<14:0>
{Transmit<5:0>, Receive<8:0>}
Transmit
Logic
Bit
Timing
Logic
TX RX
Configuration
Registers
Clock
Generator
BUFFERS
ENGINE
MODE 0
MODE 1, 2
RXF15
V
CC