Datasheet

 2010-2012 Microchip Technology Inc. DS39977F-page 369
PIC18F66K80 FAMILY
23.7 A/D Conversions
Figure 23-6 shows the operation of the A/D Converter
after the GO/DONE
bit has been set and the
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
Figure 23-7 shows the operation of the A/D Converter
after the GO/DONE
bit has been set, the ACQT<2:0>
bits set to ‘
010’ and a 4 TAD acquisition time selected.
Clearing the GO/DONE
bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. This means the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2T
AD wait is required before the next acquisition can be
started. After this wait, acquisition on the selected
channel is automatically started.
FIGURE 23-6: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
FIGURE 23-7: A/D CONVERSION T
AD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
TAD1 TAD2
TAD3
TAD4TAD5
TAD6 TAD7
TAD8
TAD11
Set GO/DONE bit
Holding capacitor is disconnected from analog input (typically 100 ns)
T
AD9 TAD10
TCY - TAD
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion starts
b2
b11
b8
b7
b6
b5
b4
b3
b10
b9
TAD13TAD12
b0b1
1
2
3 4 5
6
7
8
11
Set GO/DONE bit
(Holding capacitor is disconnected)
9
10
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.
Conversion starts
1
2
3 4
(Holding capacitor continues
acquiring input)
T
ACQT Cycles
TAD Cycles
Automatic
Acquisition
Time
b2b11
b8
b7 b6
b5
b4
b3
b10
b9
13
12
b0b1