Datasheet

 2010-2012 Microchip Technology Inc. DS39977F-page 365
PIC18F66K80 FAMILY
FIGURE 23-4: A/D BLOCK DIAGRAM
VREF+
Reference
Voltage
VNCFG
CHS<4:0>
AN14
(1)
AN13
(1)
AN4
AN3
AN2
AN1
AN0
01110
01101
00100
00011
00010
00001
00000
12-Bit
A/D
VREF-
VSS
(2,4)
Converter
1.024V Band Gap
V
DDCORE
(MUX Disconnected)
(3)
(Unimplemented)
11111
11110
11101
11100
11011
11010
11001
11000
Note 1: Channels, AN14 through AN11, and AN7 through AN5, are implemented only on 40/44-pin and 64-pin devices.
For 28-pin devices, the corresponding ANSELx bits are still implemented for those channels, but have no effect.
2: I/O pins have diode protection to VDD and VSS.
3: Channel 28 turns off analog MUX switches to allow for minimum capacitive loading of A/D inputs for finer
resolution CTMU time measurements.
4: I/O pins have diode protection to VDD and VSS.
(Unimplemented)
(Unimplemented)
(Unimplemented)
Negative Input Voltage
Positive Input Voltage
CHSN<2:0>
AN6
AN5
AN0
AV
SS
(4)
111
110
001
000
AN2
VCFG<1:0>
AN3
V
DD
(4)
11
10
01
00
Reserved
Temperature Diode
Internal V
REF+
(4.1V)
Internal V
REF+
(2.0V)