Datasheet

 2010-2012 Microchip Technology Inc. DS39977F-page 361
PIC18F66K80 FAMILY
23.2.2 A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is where the 12-bit
A/D result and extended sign bits (ADSGNx) are
loaded at the completion of a conversion. This register
pair is 16 bits wide. The A/D module gives the flexibility
of left or right justifying the 12-bit result in the 16-bit
result register. The A/D Format Select bit (ADFM) con-
trols this justification.
Figure 23-3 shows the operation of the A/D result
justification and the location of the sign bit (ADSGNx).
The extended sign bits allow for easier 16-bit math to
be performed on the result. The results are
represented as a two's compliment binary value. This
means that when sign bits and magnitude bits are
considered together in right justification, the ADRESH
and ADRESL registers can be read as a single signed
integer value.
When the A/D Converter is disabled, these 8-bit
registers can be used as two general purpose
registers.
FIGURE 23-3: A/D RESULT JUSTIFICATION
Result bits ADSGN bit
ADRESH ADRESL ADRESH ADRESL
12-Bit Result
Left Justified
ADFM =
0
Right Justified
ADFM =
1
Two’s Complement Example Results Number Line
Left Justified Right Justified
Hex Decimal Hex Decimal
0xFFF0 4095 0x0FFF 4095
0xFFE0 4094 0x0FFE 4094
…………
0x0020 2 0x0002 2
0x0010 1 0x0001 1
0x0000 0 0x0000 0
0xFFFF -1 0xFFFF -1
0xFFEF -2 0xFFFE -2
…………
0x001F -4095 0xF001 -4095
0x000F -4096 0xF000 -4096