Datasheet

PIC18F66K80 FAMILY
DS39977F-page 358  2010-2012 Microchip Technology Inc.
23.2 A/D Registers
23.2.1 A/D CONTROL REGISTERS
REGISTER 23-1: ADCON0: A/D CONTROL REGISTER 0
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-2
CHS<4:0>: Analog Channel Select bits
00000 = Channel 00 (AN0) 10000 =(Reserved)
(2)
00001 = Channel 01 (AN1) 10001 =(Reserved)
(2)
00010 = Channel 02 (AN2) 10010 =(Reserved)
(2)
00011 = Channel 03 (AN3) 10011 =(Reserved)
(2)
00100 = Channel 04 (AN4) 10100 =(Reserved)
(2)
00101 = Channel 05 (AN5)
(1,2)
10101 =(Reserved)
(2)
00110 = Channel 06 (AN6)
(1,2)
10110 =(Reserved)
(2)
00111 = Channel 07 (AN7)
(1,2)
10111 =(Reserved)
(2)
01000 = Channel 08 (AN8) 11000 =(Reserved)
(2)
01001 = Channel 09 (AN9) 11001 =(Reserved)
(2)
01010 = Channel 10 (AN10) 11010 =(Reserved)
(2)
01011 =(Reserved)
(2)
11011 =(Reserved)
(2)
01100 =(Reserved)
(2))
11100 = (MUX disconnect)
(3)
01101 =(Reserved)
(2))
11101 = Channel 29 (temperature diode)
01110 =(Reserved)
(2))
11110 = Channel 30 (VDDCORE)
01111 =(Reserved)
(2)
11111 = Channel 31 (1.024V band gap)
bit 1
GO/DONE: A/D Conversion Status bit
1 = A/D cycle is in progress. Setting this bit starts an A/D conversion cycle. The bit is cleared
automatically by hardware when the A/D conversion is completed.
0 = A/D conversion has completed or is not in progress
bit 0
ADON: A/D On bit
1 = A/D Converter is operating
0 = A/D conversion module is shut off and consuming no operating current
Note 1: These channels are not implemented on 28-pin devices.
2: Performing a conversion on unimplemented channels will return random values.
3: Channel 28 turns off analog MUX switches to allow for minimum capacitive loading of the A/D input, for
finer resolution CTMU time measurements.