Datasheet

PIC18F66K80 FAMILY
DS39977F-page 324  2010-2012 Microchip Technology Inc.
FIGURE 21-24: I
2
C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
P
9
87
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4
A3 A2 A1
SDA SCL
12
3
4
5
6
7
8
9
12
3
4
5
678 9
1234
Bus master terminates
transfer
ACK
Receiving Data from Slave
Receiving Data from Slave
D0
D1
D2
D3D4
D5
D6D7
ACK
R/W = 1
Transmit Address to Slave
SSPIF BF
ACK is not sent
Write to SSPCON2<0> (SEN = 1),
Write to SSPBUF occurs here,
ACK from Slave
Master configured as a receiver by programming SSPCON2<3> (RCEN = 1)
PEN bit = 1 written here
Data shifted in on falling edge of CLK
Cleared in software
start XMIT
SEN = 0
SSPOV
SDA = 0, SCL = 1, while CPU
(SSPSTAT<0>)
ACK
Cleared in software
Cleared in software
Set SSPIF interrupt at end of receive
Set P bit (SSPSTAT<4>) and SSPIF
ACK from master,
Set SSPIF at end
Set SSPIF interrupt at end of Acknowledge sequence
Set SSPIF interrupt at end of Acknowledge sequence
of receive
Set ACKEN, start Acknowledge sequence, SDA = ACKDT = 1
RCEN cleared automatically
RCEN = 1, start next receive
Write to SSPCON2<4> to start Acknowledge sequence, SDA = ACKDT (SSPCON2<5>) = 0
RCEN cleared automatically
responds to SSPIF
ACKEN
begin Start condition
Cleared in software
SDA = ACKDT = 0
Last bit is shifted into SSPSR and contents are unloaded into SSPBUF
Cleared in software
SSPOV is set because SSPBUF is still full