Datasheet

 2010-2012 Microchip Technology Inc. DS39977F-page 283
PIC18F66K80 FAMILY
REGISTER 20-5: PSTR1CON: PULSE STEERING CONTROL
(1)
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
CMPL1 CMPL0
— STRSYNC STRD STRC STRB STRA
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
CMPL<1:0>: Complementary Mode Output Assignment Steering Sync bits
00 = See STR<D:A>.
01 = PA and PB are selected as the complementary output pair
10 = PA and PC are selected as the complementary output pair
11 = PA and PD are selected as the complementary output pair
bit 5
Unimplemented: Read as ‘0’
bit 4
STRSYNC: Steering Sync bit
1 = Output steering update occurs on the next PWM period
0 = Output steering update occurs at the beginning of the instruction cycle boundary
bit 3
STRD: Steering Enable bit D
1 = P1D pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1D pin is assigned to port pin
bit 2
STRC: Steering Enable bit C
1 = P1C pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1C pin is assigned to port pin
bit 1
STRB: Steering Enable bit B
1 = P1B pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1B pin is assigned to port pin
bit 0
STRA: Steering Enable bit A
1 = P1A pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1A pin is assigned to port pin
Note 1: The PWM Steering mode is available only when the CCP1CON register bits, CCP1M<3:2> = 11 and
P1M<1:0> =
00.