Datasheet

PIC18F66K80 FAMILY
DS39977F-page 282  2010-2012 Microchip Technology Inc.
20.4.7 PULSE STEERING MODE
In Single Output mode, pulse steering allows any of the
PWM pins to be the modulated signal. Additionally, the
same PWM signal can simultaneously be available on
multiple pins.
Once the Single Output mode is selected
(CCP1M<3:2> =
11 and P1M<1:0> = 00 of the
CCP1CON register), the user firmware can bring out
the same PWM signal to one, two, three or four output
pins by setting the appropriate STR<D:A> bits
(PSTR1CON<3:0>), as provided in Table 20-2.
While the PWM Steering mode is active, the
CCP1M<1:0> bits (CCP1CON<1:0>) select the PWM
output polarity for the P1<D:A> pins.
The PWM auto-shutdown operation also applies to the
PWM Steering mode, as described in
Section 20.4.4
“Enhanced PWM Auto-shutdown mode”
. An
auto-shutdown event will only affect pins that have
PWM outputs enabled.
REGISTER 20-4: ECCP1DEL: ENHANCED PWM CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7
P1RSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCP1ASE bit clears automatically once the shutdown event goes
away; the PWM restarts automatically
0 = Upon auto-shutdown, ECCP1ASE must be cleared by software to restart the PWM
bit 6-0
P1DC<6:0>: PWM Delay Count bits
P1DCn = Number of F
OSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal
should transition active and the actual time it does transition active.
Note: The associated TRIS bits must be set to
output (‘
0’) to enable the pin output driver
in order to see the PWM signal on the pin.