Datasheet

 2010-2012 Microchip Technology Inc. DS39977F-page 271
PIC18F66K80 FAMILY
20.4 PWM (Enhanced Mode)
The Enhanced PWM mode can generate a PWM signal
on up to four different output pins with up to 10 bits of
resolution. It can do this through four different PWM
Output modes:
• Single PWM
• Half-Bridge PWM
• Full-Bridge PWM, Forward mode
• Full-Bridge PWM, Reverse mode
To select an Enhanced PWM mode, the P1M bits of the
CCP1CON register must be set appropriately.
The PWM outputs are multiplexed with I/O pins and are
designated: P1A, P1B, P1C and P1D. The polarity of the
PWM pins is configurable and is selected by setting the
CCP1M bits in the CCP1CON register appropriately.
Table 20-1 provides the pin assignments for each
Enhanced PWM mode.
Figure 20-3 provides an example of a simplified block
diagram of the Enhanced PWM module.
FIGURE 20-3: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
Note: To prevent the generation of an
incomplete waveform when the PWM is
first enabled, the ECCP module waits until
the start of a new PWM period before
generating a PWM signal.
Note 1: The TRIS register value for each PWM output must be configured appropriately.
2: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(1)
RQ
S
Duty Cycle Registers
DC1B<1:0>
Clear Timer2,
Toggle PWM Pin and
Latch Duty Cycle
Note 1: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create
the 10-bit time base.
TRIS
ECCP1/Output Pi
n
TRIS
Output Pi
n
TRIS
Output Pi
n
TRIS
Output Pi
n
Output
Controller
P1M<1:0>
2
CCP1M<3:0>
4
ECCP1DEL
ECCP1/P1A
P1B
P1C
P1D