Datasheet

PIC18F66K80 FAMILY
DS39977F-page 220  2010-2012 Microchip Technology Inc.
FIGURE 14-7: TIMER1 GATE SINGLE PULSE AND TOGGLE COMBINED MODE
TABLE 14-5: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
PIR1
PSPIF ADIF RC1IF TX1IF SSPIF TMR1GIF TMR2IF TMR1IF
PIE1
PSPIE ADIE RC1IE TX1IE SSPIE TMR1GIE TMR2IE TMR1IE
IPR1
PSPIP ADIP RC1IP TX1IP SSPIP TMR1GIP TMR2IP TMR1IP
TMR1L Timer1 Register Low Byte
TMR1H Timer1 Register High Byte
T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 SOSCEN T1SYNC
RD16 TMR1ON
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
T1DONE
T1GVAL T1GSS1 T1GSS0
OSCCON2
— SOSCRUN — SOSCDRV SOSCGO — MFIOFS MFIOSEL
PMD1
PSPMD CTMUMD ADCMD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD
Legend: Shaded cells are not used by the Timer1 module.
TMR1GE
T1GPOL
T1G_IN
T1CKI
T1GVAL
Timer1
N
N + 1
N + 2
T1GSPM
T1GGO/
T1DONE
Set by Software
Cleared by Hardware on
Falling Edge of T1GVAL
T1GTM
Counting Enabled on
Rising Edge of T1G
N + 4
N + 3