Datasheet

 2010-2012 Microchip Technology Inc. DS39977F-page 213
PIC18F66K80 FAMILY
FIGURE 14-1: TIMER1 BLOCK DIAGRAM
TMR1H TMR1L
T1SYNC
T1CKPS<1:0>
Prescaler
1, 2, 4, 8
0
1
Synchronized
Clock Input
2
Set Flag bit,
TMR1IF, on
Overflow
TMR1
(2)
TMR1ON
Note 1: ST Buffer is high-speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
4: The output of SOSC is determined by the SOSCSEL<1:0> Configuration bits.
T1G
SOSC
F
OSC/4
Internal
Clock
SOSCO/SCLKI
SOSCI
1
0
T1CKI
TMR1CS<1:0>
(1)
Synchronize
(3)
det
Sleep Input
TMR1GE
0
1
00
01
10
11
From TMR2
From Comparator 1
T1GPOL
D
Q
CK
Q
0
1
T1GVAL
T1GTM
T1GSPM
T1GGO/T1DONE
T1GSS<1:0>
EN
OUT
(4)
10
00
01
FOSC
Internal
Clock
From Comparator 2
Match PR2
R
D
EN
Q
Q1
RD
T1GCON
Data Bus
TMR1GIF
Set
T1CLK
FOSC/2
Internal
Clock
D
EN
Q
T1G_IN
TMR1ON
Output
Output
T1CON.SOSCEN
T3CON.SOSCEN
SOSCGO
SCS<1:0> = 01
Interrupt
det
Single Pulse
Acq. Control