Datasheet

PIC18F66K80 FAMILY
DS39977F-page 196  2010-2012 Microchip Technology Inc.
FIGURE 12-1: SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR
D
Q
MDBIT
MDMIN
MSSP (SDO)
EUSART1 (TX)
EUSART2 (TX)
ECCP1
CCP2
CCP3
Reserved
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
No Channel
Selected
V SS
MDCIN1
MDCIN2
REFO Clock
ECCP1
CCP2
CCP3
CCP4
0000
0001
0010
0011
0100
0101
0110
0111
1000
1111
1001
* *
Reserved
No Channel Selected
V SS
MDCIN1
MDCIN2
REFO Clock
ECCP1
CCP2
CCP3
CCP4
0000
0001
0010
0011
0100
0101
0110
0111
1000
1111
MDCH<3:0>
MDMS<3:0>
MDCL<3:0>
1111
*
*
CCP4
CCP5
SYNC
MDCHPOL
MDCLPOL
D
Q
1
0
SYNC
1
0
MDCHSYNC
MDCLSYNC
MDOUT
MDOPOL
MDOE
CARH
CARL
EN
MDEN
Data Signal
Modulator
MOD
CCP5
1001
CCP5
* *
Reserved
No Channel Selected