Datasheet

PIC18F66K80 FAMILY
DS39977F-page 190  2010-2012 Microchip Technology Inc.
11.8 PORTG, TRISG and
LATG Registers
PORTG is a 5-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISG and LATG.
PORTG is multiplexed with EUSARTx and CCP, ECCP,
Analog, Comparator and Timer input functions
(Table 11-13). When operating as I/O, all PORTG pins
have Schmitt Trigger input buffers. The open-drain
functionality for the EUARTx can be configured using
ODCON.
Each of the PORTG pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is per-
formed by clearing bit, RGPU (PADCFG1<4>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings. The pin override value is not loaded into
the TRIS register. This allows read-modify-write of the
TRIS register without concern due to peripheral
overrides.
EXAMPLE 11-7: INITIALIZING PORTG
Note: PORTG is only available on 64-pin
devices.
CLRF PORTG ; Initialize PORTG by
; clearing output
; data latches
CLRF LATG ; Alternate method
; to clear output
; data latches
MOVLW 04h ; Value used to
; initialize data
; direction
MOVWF TRISG ; Set RG1:RG0 as
; outputs
; RG2 as input
; RG4:RG3 as inputs
TABLE 11-13: PORTG FUNCTIONS
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
RG0/RX1/DT1 RG0 0 O DIG LATG<0> data output.
1 I ST PORTG<0> data input.
RX1 1 I ST Asynchronous serial receive data input (EUSARTx module).
DT1 0 O DIG Synchronous serial data output (EUSARTx module); takes priority over port data.
1 I ST Synchronous serial data input (EUSARTx module); user must configure
as an input.
RG1/CANTX RG1 0 O DIG LATG<1> data output.
1 I ST PORTG<1> data input.
CANTX 0 O DIG CAN bus TX.
RG2/T3CKI RG2 0 O DIG LATG<2> data output.
1 I ST PORTG<2> data input.
T3CKI
(2)
x I ST Timer3 clock input.
RG3/TX1/CK1 RG3 0 O DIG LATG<3> data output.
1 I ST PORTG<3> data input.
TX1 0 O DIG Asynchronous serial data output (EUSARTx module); takes priority over port data.
CK1 0 O DIG Synchronous serial clock output (EUSARTx module); user must
configure as an input.
1 I ST Synchronous serial clock input (EUSARTx module); user must configure
as an input.
RG4/T0CKI RG4 0 O DIG LATG<4> data output.
1 I ST PORTG<4> data input.
T0CKI
(1)
x I ST Timer0 clock input.
Legend: O = Output; I = Input; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Note 1: This is the alternate pin assignment for T0CKI on 64-pin devices when the T0CKMX Configuration bit is cleared.
2: This is the default pin assignment for T3CKI on 64-pin devices when the T3CKMX Configuration bit is set.