Datasheet

PIC18F66K80 FAMILY
DS39977F-page 186  2010-2012 Microchip Technology Inc.
TABLE 11-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
RD7/RX2/DT2/
P1D/PSP7
RD7 0 O DIG LATD<7> data output.
1 I ST PORTD<7> data input.
RX2
(1)
1 I ST Asynchronous serial receive data input (EUSARTx module).
DT2
(1)
1 O DIG Synchronous serial data output (EUSARTx module); takes priority over
port data.
1 I ST Synchronous serial data input (EUSARTx module); user must
configure as an input.
P1D 0 O DIG ECCP1 Enhanced PWM output, Channel D. May be configured for
tri-state during Enhanced PWM.
PSP7 x I/O ST Parallel Slave Port data.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0
TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
PADCFG1 RDPU
(1)
REPU
(1)
RFPU
(2)
RGPU
(2)
— — — CTMUDS
ODCON
SSPOD CCP5OD CCP4OD CCP3OD CCP2OD CCP1OD U2OD U1OD
ANCON1
— ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8
Legend: Shaded cells are not used by PORTD.
Note 1: These bits are unimplemented on 28-pin devices, read as ‘0’.
2: These bits are unimplemented on 28/40/44-pin devices, read as ‘0’.
TABLE 11-7: PORTD FUNCTIONS (CONTINUED)
Pin Name Function
TRIS
Setting
I/O I/O Type Description
Legend: O = Output; I = Input; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Note 1: This is the pin assignment for 40 and 44-pin devices (PIC18F4XK80).