Datasheet

PIC18F66K80 FAMILY
DS39977F-page 182  2010-2012 Microchip Technology Inc.
TABLE 11-5: PORTC FUNCTIONS
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
RC0/SOSCO/
SCLKI
RC0 0 O DIG LATC<0> data output.
1 I ST PORTC<0> data input.
SOSCO 1 I ST SOSC oscillator output.
SCLKI 1 I ST Digital clock input; enabled when SOSC oscillator is disabled.
RC1/SOSCI RC1 0 O DIG LATC<1> data output.
1 I ST PORTC<1> data input.
SOSCI x I ANA SOSC oscillator input.
RC2/T1G/
CCP2
RC2 0 O DIG LATC<2> data output.
1 I ST PORTC<2> data input.
T1G x I ST Timer1 external clock gate input.
CCP2 0 O DIG CCP2 compare/PWM output; takes priority over port data.
1 I ST CCP2 capture input.
RC3/REFO/
SCL/SCK
RC3 0 O DIG LATC<3> data output.
1 I ST PORTC<3> data input.
REFO x O DIG Reference output clock.
SCL 0 ODIGI
2
C™ clock output (MSSP module); takes priority over port data.
1 II
2
CI
2
C clock input (MSSP module); input type depends on module setting.
SCK 0 O DIG SPI clock output (MSSP module); takes priority over port data.
1 I ST SPI clock input (MSSP module).
RC4/SDA/SDI RC4 0 O DIG LATC<4> data output.
1 I ST PORTC<4> data input.
SDA 1 ODIGI
2
C data output (MSSP module); takes priority over port data.
1 II
2
CI
2
C data input (MSSP module); input type depends on module setting.
SDI 1 I ST SPI data input (MSSP module).
RC5/SDO RC5 0 O DIG LATC<5> data output.
1 I ST PORTC<5> data input.
SDO 0 O DIG SPI data output (MSSP module).
RC6/CANTX/
TX1/CK1/
CCP3
RC6 0 O DIG LATC<6> data output.
1 I ST PORTC<6> data input.
CANTX
(2)
0 O DIG CAN bus TX.
TX1
(1)
0 O DIG Asynchronous serial data output (EUSARTx module); takes priority over port data.
CK1
(1)
0 ODIG Synchronous serial clock output (EUSARTx module); user must configure as an input.
1 I ST Synchronous serial clock input (EUSARTx module); user must configure as an input.
CCP3 0 O DIG CCP3 compare/PWM output. Takes priority over port data.
1 I ST CCP3 capture input.
Legend: O = Output; I = Input; I
2
C = I
2
C/SMBus; ANA = Analog Signal; DIG = CMOS Output; ST = Schmitt Trigger Buffer Input; x
= Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Note 1: The pin assignment for 28, 40 and 44-pin devices (PIC18F2XK80 and PIC18F4XK80).
2: The alternate pin assignment for CANRX and CANTX on 28, 40 and 44-pin devices (PIC18F4XK80) when the CANMX
Configuration bit is set.