Datasheet

PIC18F66K80 FAMILY
DS39977F-page 172  2010-2012 Microchip Technology Inc.
REGISTER 11-1: PADCFG1: PAD CONFIGURATION REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0
RDPU
(1)
REPU
(1)
RFPU
(2)
RGPU
(2)
— — — CTMUDS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7
RDPU: PORTD Pull-up Enable bit
(1)
1 = PORTD pull-up resistors are enabled by individual port latch values
0 = All PORTD pull-up resistors are disabled
bit 6
REPU: PORTE Pull-up Enable bit
(1)
1 = PORTE pull-up resistors are enabled by individual port latch values
0 = All PORTE pull-up resistors are disabled
bit 5
RFPU: PORTF Pull-up Enable bit
(2)
1 = PORTF pull-up resistors are enabled by individual port latch values
0 = All PORTF pull-up resistors are disabled
bit 4
RGPU: PORTG Pull-up Enable bit
(2)
1 = PORTG pull-up resistors are enabled by individual port latch values
0 = All PORTG pull-up resistors are disabled
bit 3-1
Unimplemented: Read as ‘0’
bit 0
CTMUDS: CTMU Comparator Data Select bit
1 = External comparator (with output on pin CTDIN) is used for CTMU compares
0 = Internal comparator (CMP2) is used for CTMU compares
Note 1: These bits are unimplemented on 28-pin devices.
2: These bits are unimplemented on 40-pin devices.
REGISTER 11-2: WPUB: WEAK PULL-UP PORTB ENABLE REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
WPUB<7:0>: Weak Pull-Up Enable Register bits
1 = Pull-up is enabled on corresponding PORTB pin when RBPU = 0 and the pin is an input
0 = Pull-up is disabled on corresponding PORTB pin