Datasheet

 2010-2012 Microchip Technology Inc. DS39977F-page 17
PIC18F66K80 FAMILY
FIGURE 1-3: PIC18F6XK80 (64-PIN) BLOCK DIAGRAM
Instruction
Decode and
Control
Data Latch
Data Memory
(2/4 Kbytes)
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
PCLATU
PCU
Note 1: See Tab l e 1 -6 for I/O port pin descriptions.
2: RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section 3.0 “Oscillator
Configurations”.
3: RE3 is only available when the MCLRE Configuration bit is cleared (MCLRE = 0).
EUSART1
Comparator
CTMU
Timer1
A/D
12-Bit
W
Instruction Bus<16>
STKPTR
Bank
8
State Machine
Control Signals
Decode
8
8
EUSART2
ROM Latch
PORTC
PORTD
PORTF
PORTG
RC<7:0>
(1)
RD<7:0>
(1)
RF<7:0>
(1)
RG<4:0>
(1)
PORTB
RB<7:0>
(1)
OSC1/CLKI
OSC2/CLKO
V
DD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
BOR and
LVD
Precision
Reference
Band Gap
INTOSC
Oscillator
Regulator
Voltage
VDDCORE/VCAP
16 MHz
Oscillator
Timer0
Timer2/4
Timer3
1/2
CCP2/3/4/5
ECCP1
PORTA
RA<3:0>
RA<7:5>
(1,2)
PORTE
RE<7:0>
(1,3)
ECAN
DSM
PSP
MSSP