Datasheet

PIC18F66K80 FAMILY
DS39977F-page 164  2010-2012 Microchip Technology Inc.
REGISTER 10-16: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0
— — RC2IP TX2IP CTMUIP CCP2IP CCP1IP —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5
RC2IP: EUSARTx Receive Priority Flag bit
1 =High priority
0 = Low priority
bit 4
TX2IP: EUSARTx Transmit Interrupt Priority bit
1 =High priority
0 = Low priority
bit 3
CTMUIP: CTMU Interrupt Priority bit
1 =High priority
0 = Low priority
bit 2
CCP2IP: CCP2 Interrupt Priority bit
1 =High priority
0 = Low priority
bit 1
CCP1IP: ECCP1 Interrupt Priority bit
1 =High priority
0 = Low priority
bit 0
Unimplemented: Read as ‘0’