Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SSOP 28 8-Bit 64 MHz I/O number 24

 2010-2012 Microchip Technology Inc. DS39977F-page 1

Power-Managed Modes:

• Run: CPU on, Peripherals on

• Idle: CPU off, Peripherals on

• Sleep: CPU off, Peripherals off

• Two-Speed Oscillator Start-up

• Fail-Safe Clock Monitor (FSCM)

• Power-Saving Peripheral Module Disable (PMD)

• Ultra Low-Power Wake-up

• Fast Wake-up, 1 s, Typical

• Low-Power WDT, 300 nA, Typical

• Run mode Currents Down to Very Low 3.8 A, Typical

• Idle mode Currents Down to Very Low 880 nA, Typical

• Sleep mode Current Down to Very Low 13 nA, Typical

ECAN Bus Module Features:

• Conforms to CAN 2.0B Active Specification

• Three Operating modes:

- Legacy mode (full backward compatibility with

existing PIC18CXX8/FXX8 CAN modules)

- Enhanced mode

- FIFO mode or programmable TX/RX buffers

• Message Bit Rates up to 1 Mbps

• DeviceNet™ Data Byte Filter Support

• Six Programmable Receive/Transmit Buffers

• Three Dedicated Transmit Buffers with Prioritization

• Two Dedicated Receive Buffers

ECAN Bus Module Features (Continued):

• 16 Full, 29-Bit Acceptance Filters with Dynamic

Association

• Three Full, 29-Bit Acceptance Masks

• Automatic Remote Frame Handling

• Advanced Error Management Features

Special Microcontroller Features:

• Operating Voltage Range: 1.8V to 5.5V

• On-Chip 3.3V Regulator

• Operating Speed up to 64 MHz

• Up to 64 Kbytes On-Chip Flash Program Memory:

- 10,000 erase/write cycle, typical

- 20 years minimum retention, typical

• 1,024 Bytes of Data EEPROM:

- 100,000 Erase/write cycle data EEPROM

memory, typical

• 3.6 Kbytes of General Purpose Registers (SRAM)

• Three Internal Oscillators: LF-INTOSC (31 KHz),

MF-INTOSC (500 kHz) and HF-INTOSC (16 MHz)

• Self-Programmable under Software Control

• Priority Levels for Interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 4,194s

• In-Circuit Serial Programming™ (ICSP™) via Two Pins

• In-Circuit Debug via Two Pins

• Programmable BOR

• Programmable LVD

TABLE 1: DEVICE COMPARISON

Device

Program

Memory

Data

Memory

(Bytes)

Data EE

(Bytes)

Pins I/O

CTMU

12-Bit A/D

Channels

CCP/

ECCP

Timers

8-Bit/16-Bit

EUSART

Comparators

ECAN™

MSSP

BORMV/LVD

DSM

PIC18F25K80 32 Kbytes 3,648 1,024 28 24 1 8-ch 4/1 2/3 2 2 1 1 Yes No

PIC18LF25K80 32 Kbytes 3,648 1,024 28 24 1 8-ch 4/1 2/3 2 2 1 1 Yes No

PIC18F26K80 64 Kbytes 3,648 1,024 28 24 1 8-ch 4/1 2/3 2 2 1 1 Yes No

PIC18LF26K80 64 Kbytes 3,648 1,024 28 24 1 8-ch 4/1 2/3 2 2 1 1 Yes No

PIC18F45K80 32 Kbytes 3,648 1,024 40/44 35 1 11-ch 4/1 2/3 2 2 1 1 Yes No

PIC18LF45K80 32 Kbytes 3,648 1,024 40/44 35 1 11-ch 4/1 2/3 2 2 1 1 Yes No

PIC18F46K80 64 Kbytes 3,648 1,024 40/44 35 1 11-ch 4/1 2/3 2 2 1 1 Yes No

PIC18LF46K80 64 Kbytes 3,648 1,024 40/44 35 1 11-ch 4/1 2/3 2 2 1 1 Yes No

PIC18F65K80 32 Kbytes 3,648 1,024 64 54 1 11-ch 4/1 2/3 2 2 1 1 Yes Yes

PIC18LF65K80 32 Kbytes 3,648 1,024 64 54 1 11-ch 4/1 2/3 2 2 1 1 Yes Yes

PIC18F66K80 64 Kbytes 3,648 1,024 64 54 1 11-ch 4/1 2/3 2 2 1 1 Yes Yes

PIC18LF66K80 64 Kbytes 3,648 1,024 64 54 1 11-ch 4/1 2/3 2 2 1 1 Yes Yes

PIC18F66K80 FAMILY

28/40/44/64-Pin, Enhanced Flash Microcontrollers

with ECAN™ and nanoWatt XLP Technology

Summary of content (622 pages)

PAGE 1
PIC18F66K80 FAMILY 28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology Power-Managed Modes: ECAN Bus Module Features (Continued): • • • • • • • • • • • • • 16 Full, 29-Bit Acceptance Filters with Dynamic Association • Three Full, 29-Bit Acceptance Masks • Automatic Remote Frame Handling • Advanced Error Management Features Run: CPU on, Peripherals on Idle: CPU off, Peripherals on Sleep: CPU off, Peripherals off Two-Speed Oscillator Start-up Fail-Safe Clock Monitor (FS
PAGE 2
PIC18F66K80 FAMILY Peripheral Highlights: • Five CCP/ECCP modules: - Four Capture/Compare/PWM (CCP) modules - One Enhanced Capture/Compare/PWM (ECCP) module • Five 8/16-Bit Timer/Counter modules: - Timer0: 8/16-bit timer/counter with 8-bit programmable prescaler - Timer1, Timer3: 16-bit timer/counter - Timer2, Timer4: 8-bit timer/counter • Two Analog Comparators • Configurable Reference Clock Output • Charge Time Measurement Unit (CTMU): - Capacitance measurement - Time measurement with 1 ns typical resolut
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PIC18F66K80 FAMILY Pin Diagrams Note 1: RB5/T0CKI/T3CKI/CCP5/KBI1 RB4/AN9/C2INA/ECCP1/P1A/CTPLS/KBI0 23 22 RB7/PGD/T3G/RX2/DT2/KBI3 MCLR/RE3 RB6/PGC/TX2/CK2/KBI2 14 RC6/CANTX/TX1/CK1/CCP3 RC4/SDA/SDI RC5/SDO RC0/SOSCO/SCLKI 8 OSC2/CLKOUT/RA6 RC3/REFO/SCL/SCK OSC1/CLKIN/RA7 5 6 7 RC2/T1G/CCP2 VSS PIC18F2XK80 PIC18LF2XK80 9 10 11 12 13 VDDCORE/VCAP RA5/AN4/C2INB/HLVDIN/T1CKI/SS/CTMUI 1 2 3 4 RC1/SOSCI RA2/VREF-/AN2 RA3/VREF+/AN3 25 24 RA0/CVREF/AN0/ULPWU 28 27 26 RA1/AN1 28-Pin QF
PAGE 4
PIC18F66K80 FAMILY Pin Diagrams (Continued) 28-Pin SSOP/SPDIP/SOIC MCLR/RE3 1 28 RB7/PGD/T3G/RX2/DT2/KBI3 RA0/CVREF/AN0/ULPWU 27 RB6/PGC/TX2/CK2/KBI2 RA1/AN1 2 3 RB5/T0CKI/T3CKI/CCP5/KBI1 RA2/VREF-/AN2 4 26 25 RA3/VREF+/AN3 5 6 24 RB3/CANRX/C2OUT/P1D/CTED2/INT3 23 RB2/CANTX/C1OUT/P1C/CTED1/INT2 22 RB1/AN8/C1INB/P1B/CTDIN/INT1 RB0/AN10/C1INA/FLT0/INT0 OSC2/CLKOUT/RA6 9 10 21 20 19 RC0/SOSCO/SCLKI 11 18 RC7/CANRX/RX1/DT1/CCP4 RC1/ISOSCI 17 16 RC6/CANTX/TX1/CK1/CCP3 RC2/T1G/CCP2
PAGE 5
PIC18F66K80 FAMILY Pin Diagrams (Continued) RD2/C2INA/PSP2 RD1/C1INB/PSP1 RD0/C1INA/PSP0 RC1/SOSCI N/C 39 38 37 36 35 34 RB1/AN8/CTDIN/INT1 9 10 11  2010-2012 Microchip Technology Inc.
PAGE 6
PIC18F66K80 FAMILY Pin Diagrams (Continued) RD1/C1INB/PSP1 RD0/C1INA/PSP0 RC1/SOSCI N/C 38 37 36 35 34 RC2/T1G/CCP2 RD2/C2INA/PSP2 39 RC3/REFO/SCL/SCK RC4/SDA/SDI 42 41 40 RB1/AN8/CTDIN/INT1 9 10 11 RC0/SOSCO/SCLKI 31 30 29 28 27 OSC2/CLKOUT/RA6 OSC1/CLKIN/RA7 26 25 24 23 RA2/VREF-/AN2/C2INC RA1/AN1/C1INC RA0/CVREF/AN0/ULPWU 13 14 15 16 17 N/C 32 18 19 20 21 22 12 N/C N/C PIC18F4XK80 PIC18LF4XK80 33 VSS VDD RE2/AN7/C2OUT/CS RE1/AN6/C1OUT/WR RE0/AN5/RD RA5/AN4/HLVDIN/T1CKI/SS VD
PAGE 7
PIC18F66K80 FAMILY Pin Diagrams (Continued) RC7/CCP4 RD4/ECCP1/P1A/PSP4 RD5/P1B/PSP5 RD6/P1C/PSP6 RD7/P1D/PSP7 RG0/RX1/DT1 RG1/CANTX2 VSS AVDD VDD RG2/T3CKI RG3/TX1/CK1 RB0/AN10/FLT0/INT0 RB1/AN8/CTDIN/INT1 RB2/CANTX/CTED1/INT2 RC1/SOSCI RC2/T1G/CCP2 RC3/REFO/SCL/SCK RF6/MDOUT RF7 RD0/C1INA/PSP0 RD1/C1INB/PSP1 VSS VDD RD2/C2INA/PSP2 RD3/C2INB/CTMUI/PSP3 RC4/SDA/SDI 62 61 60 RE6/RX2/DT2 RC5/SDO 63 59 58 57 56 55 54 53 52 51 50 49 RC6/CCP3 64 48 47 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
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PIC18F66K80 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started with PIC18FXXKXX Microcontrollers ......................................................................................... 45 3.0 Oscillator Configurations ...........................................................................................
PAGE 9
PIC18F66K80 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PAGE 10
PIC18F66K80 FAMILY NOTES: DS39977F-page 10  2010-2012 Microchip Technology Inc.
PAGE 11
PIC18F66K80 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • • • • • • PIC18F25K80 PIC18F26K80 PIC18F45K80 PIC18F46K80 PIC18F65K80 PIC18F66K80 • • • • • • PIC18LF25K80 PIC18LF26K80 PIC18LF45K80 PIC18LF46K80 PIC18LF65K80 PIC18LF66K80 This family combines the traditional advantages of all PIC18 microcontrollers – namely, high computational performance and a rich feature set – with an extremely competitive price point.
PAGE 12
PIC18F66K80 FAMILY 1.1.5 EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating to the next larger device. This is true when moving between the 28-pin, 40-pin, 44-pin and 64-pin members, or even jumping from smaller to larger memory devices.
PAGE 13
PIC18F66K80 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC18F2XK80 (28-PIN DEVICES) Features PIC18F25K80 Operating Frequency Program Memory (Bytes) Program Memory (Instructions) PIC18F26K80 DC – 64 MHz 32K 64K 16,384 Data Memory (Bytes) 32,768 3.
PAGE 14
PIC18F66K80 FAMILY TABLE 1-3: DEVICE FEATURES FOR THE PIC18F6XK80 (64-PIN DEVICES) Features PIC18F65K80 Operating Frequency Program Memory (Bytes) Program Memory (Instructions) PIC18F66K80 DC – 64 MHz 32K 64K 16,384 Data Memory (Bytes) 32,768 3.
PAGE 15
PIC18F66K80 FAMILY FIGURE 1-1: PIC18F2XK80 (28-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 8 inc/dec logic Data Memory (2/4 Kbytes) PCLATU PCLATH 21 PORTA RA<3:0> RA<7:5>(1,2) Data Latch 8 Address Latch 20 PCU PCH PCL Program Counter 12 Data Address<12> 31-Level Stack 4 BSR Address Latch STKPTR Program Memory 8 4 Access Bank 12 FSR0 FSR1 FSR2 Data Latch PORTB RB<7:0>(1) 12 PORTC RC<7:0>(1) inc/dec logic Table Latch Address Decode ROM Latch Instruction Bus<16> PORTE RE3(1,3
PAGE 16
PIC18F66K80 FAMILY FIGURE 1-2: PIC18F4XK80 (40/44-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 8 inc/dec logic Data Memory (2/4 Kbytes) PCLATU PCLATH 21 PORTA RA<3:0> RA<7:5>(1,2) Data Latch 8 Address Latch 20 PCU PCH PCL Program Counter 12 Data Address<12> 31-Level Stack 4 BSR Address Latch STKPTR Program Memory 8 4 Access Bank 12 FSR0 FSR1 FSR2 Data Latch PORTB RB<7:0>(1) 12 PORTC RC7:0>(1) inc/dec logic Table Latch Address Decode ROM Latch Instruction Bus<16> PORTD RD<7:
PAGE 17
PIC18F66K80 FAMILY FIGURE 1-3: PIC18F6XK80 (64-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> inc/dec logic Data Memory (2/4 Kbytes) PCLATU PCLATH 21 PORTA RA<3:0> RA<7:5>(1,2) Data Latch 8 8 Address Latch 20 PCU PCH PCL Program Counter 12 Data Address<12> 31-Level Stack 4 BSR Address Latch STKPTR Program Memory 8 4 Access Bank 12 FSR0 FSR1 FSR2 Data Latch PORTB RB<7:0>(1) 12 PORTC RC<7:0>(1) inc/dec logic Table Latch Address Decode ROM Latch Instruction Bus<16> PORTD RD<7:0>
PAGE 18
PIC18F66K80 FAMILY TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS Pin Number SSOP/ Pin Buffer QFN SPDIP Type Type /SOIC Pin Name 26 MCLR/RE3 Description 1 MCLR I ST Master Clear (input) or programming voltage (input). This pin is an active-low Reset to the device. RE3 I ST General purpose, input only pin. OSC1 I ST Oscillator crystal input. CLKIN I OSC1/CLKIN/RA7 6 9 RA7 I/O OSC2/CLKOUT/RA6 7 CMOS External clock source input. Always associated with pin function, OSC1.
PAGE 19
PIC18F66K80 FAMILY TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED) Pin Number SSOP/ Pin Buffer QFN SPDIP Type Type /SOIC Pin Name Description PORTA is a bidirectional I/O port. RA0/CVREF/AN0/ULPWU 27 2 RA0 I/O ST/ General purpose I/O pin. CMOS CVREF O Analog Comparator reference voltage output. AN0 I Analog Analog Input 0. ULPWU I Analog Ultra Low-Power Wake-up input. RA1/AN1 28 3 RA1 I/O AN1 I RA2/VREF-/AN2 1 ST/ Digital I/O. CMOS Analog Analog Input 1.
PAGE 20
PIC18F66K80 FAMILY TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED) Pin Number SSOP/ Pin Buffer QFN SPDIP Type Type /SOIC Pin Name Description PORTB is a bidirectional I/O port. RB0/AN10/C1INA/FLT0/ INT0 18 21 RB0 I/O ST/ Digital I/O. CMOS AN10 I Analog Analog Input 10. C1INA I Analog Comparator 1 Input A. FLT0 I ST Enhanced PWM Fault input for ECCP1. INT0 I ST External Interrupt 0. RB1/AN8/C1INB/P1B/ CTDIN/INT1 19 22 RB1 I/O AN8 I Analog Analog Input 8.
PAGE 21
PIC18F66K80 FAMILY TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED) Pin Number SSOP/ Pin Buffer QFN SPDIP Type Type /SOIC Pin Name RB4/AN9/C2INA/ECCP1/ P1A/CTPLS/KBI0 22 Description 25 RB4 I/O AN9 I Analog Analog Input 9. C2INA I Analog Comparator 2 Input A. ECCP1 I/O P1A O CTPLS O ST CTMU pulse generator output. I ST Interrupt-on-change pin. KBI0 RB5/T0CKI/T3CKI/CCP5/ KBI1 23 ST/ Digital I/O. CMOS ST Capture 1 input/Compare 1 output/PWM1 output.
PAGE 22
PIC18F66K80 FAMILY TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED) Pin Number SSOP/ Pin Buffer QFN SPDIP Type Type /SOIC Pin Name Description PORTC is a bidirectional I/O port. RC0/SOSCO/SCLKI 8 11 RC0 I/O SOSCO SCLKI RC1/SOSCI 9 I ST Timer1 oscillator output. I ST Digital SOSC input. 12 RC1 I/O SOSCI I RC2/T1G/CCP2 10 ST/ Digital I/O. CMOS ST/ Digital I/O. CMOS CMOS SOSC oscillator input. 13 RC2 I/O T1G I ST Timer1 external clock gate input.
PAGE 23
PIC18F66K80 FAMILY TABLE 1-4: PIC18F2XK80 I/O DESCRIPTIONS (CONTINUED) Pin Number SSOP/ Pin Buffer QFN SPDIP Type Type /SOIC Pin Name RC7/CANRX/RX1/DT1/ CCP4 15 Description 18 RC7 I/O CANRX ST/ Digital I/O. CMOS I ST CAN bus RX. RX1 I ST EUSART asynchronous receive. DT1 I/O ST EUSART synchronous data. (See related TX2/CK2.) CCP4 I/O VSS 5 8 16 19 3 6 P VSS VSS Ground reference for logic and I/O pins. VSS VDDCORE/VCAP ST Capture 4 input/Compare 4 output/PWM4 output.
PAGE 24
PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP MCLR/RE3 1 Pin Buffer QFN/ Type Type TQFP Description 18 MCLR I ST Master Clear (input) or programming voltage (input). This pin is an active-low Reset to the device. RE3 I ST General purpose, input only pin. OSC1 I ST Oscillator crystal input. CLKIN I OSC1/CLKIN/RA7 13 30 RA7 OSC2/CLKOUT/RA6 I/O 14 CMOS External clock source input. Always associated with pin function, OSC1.
PAGE 25
PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP Pin Buffer QFN/ Type Type TQFP Description PORTA is a bidirectional I/O port. RA0/CVREF/AN0/ULPWU 2 19 RA0 I/O ST/ General purpose I/O pin. CMOS CVREF O Analog Comparator reference voltage output. AN0 I Analog Analog Input 0. ULPWU I Analog Ultra Low-Power Wake-up input. RA1/AN1/C1INC 3 20 RA1 I/O ST/ Digital I/O. CMOS AN1 I Analog Analog Input 1.
PAGE 26
PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP Pin Buffer QFN/ Type Type TQFP Description PORTB is a bidirectional I/O port. RB0/AN10/FLT0/INT0 33 8 RB0 I/O AN10 I FLT0 I ST Enhanced PWM Fault input for ECCP1. INT0 I ST External Interrupt 0. RB1/AN8/CTDIN/INT1 34 ST/ Digital I/O. CMOS Analog Analog Input 10. 9 RB1 I/O ST/ Digital I/O. CMOS AN8 I CTDIN I ST CTMU pulse delay input. INT1 I ST External Interrupt 1.
PAGE 27
PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP RB6/PGC/KBI2 Pin Buffer QFN/ Type Type TQFP 39 Description 16 RB6 I/O PGC I ST In-Circuit Debugger and ICSP™ programming clock input pin. KBI2 I ST Interrupt-on-change pin. RB7/PGD/T3G/KBI3 40 ST/ Digital I/O. CMOS 17 RB7 I/O PGD I/O ST In-Circuit Debugger and ICSP™ programming data pin. T3G I ST Timer3 external clock gate input. KBI3 I ST Interrupt-on-change pin.
PAGE 28
PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP Pin Buffer QFN/ Type Type TQFP Description PORTC is a bidirectional I/O port. RC0/SOSCO/SCLKI 15 32 RC0 I/O SOSCO SCLKI RC1/SOSCI 16 I ST SOSC oscillator output. I ST Digital SOSC input. 35 RC1 I/O SOSCI I RC2/T1G/CCP2 17 ST/ Digital I/O. CMOS ST/ Digital I/O. CMOS CMOS SOSC oscillator input. 36 RC2 I/O T1G I CCP2 ST/ Digital I/O. CMOS ST Timer1 external clock gate input.
PAGE 29
PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP RC7/CANRX/RX1/DT1/ CCP4 Pin Buffer QFN/ Type Type TQFP 26 RC7 Description 1 I/O ST/ Digital I/O. CMOS CANRX I ST CAN bus RX. RX1 I ST EUSART asynchronous receive. DT1 I/O ST EUSART synchronous data. (See related TX2/CK2.) CCP4 I/O ST Capture 4 input/Compare 4 output/PWM4 output.
PAGE 30
PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP Pin Buffer QFN/ Type Type TQFP Description PORTD is a bidirectional I/O port. RD0/C1INA/PSP0 19 38 RD0 I/O ST/ Digital I/O. CMOS C1INA I PSP0 I/O ST/ Parallel Slave Port data. CMOS I/O ST/ Digital I/O. CMOS RD1/C1INB/PSP1 20 Analog Comparator 1 Input A. 39 RD1 C1INB I PSP1 I/O ST/ Parallel Slave Port data. CMOS I/O ST/ Digital I/O.
PAGE 31
PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP RD6/TX2/CK2/P1C/PSP6 Pin Buffer QFN/ Type Type TQFP 29 Description 4 RD6 I/O ST/ Digital I/O. CMOS TX2 I ST EUSART asynchronous transmit. CK2 I/O ST EUSART synchronous clock. (See related RX2/DT2.) P1C O CMOS Enhanced PWM1 Output C. PSP6 I/O ST/ Parallel Slave Port data. CMOS RD7 I/O ST/ Digital I/O. CMOS RX2 I DT2 I/O P1D O CMOS Enhanced PWM1 Output D.
PAGE 32
PIC18F66K80 FAMILY TABLE 1-5: PIC18F4XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP VSS Pin Buffer QFN/ Type Type TQFP 12 29 31 6 Description P VSS Ground reference for logic and I/O pins. VSS Ground reference for logic and I/O pins. VSS VDDCORE/VCAP 6 23 P VDDCORE External filter capacitor connection VCAP External filter capacitor connection VDD 11 28 P 32 7 P VDD Positive supply for logic and I/O pins. VDD VDD Positive supply for logic and I/O pins.
PAGE 33
PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS Pin Name MCLR/RE3 Pin Num Pin Type Buffer Type I ST Master Clear (input) or programming voltage (input). This pin is an active-low Reset to the device. I ST General purpose, input only pin. ST Oscillator crystal input. 28 MCLR RE3 OSC1/CLKIN/RA7 46 OSC1 I CLKIN I RA7 OSC2/CLKOUT/RA6 Description I/O CMOS External clock source input. Always associated with pin function, OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.
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PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Num Pin Type Buffer Type Description PORTA is a bidirectional I/O port. RA0/CVREF/AN0/ ULPWU 29 RA0 I/O ST/ General purpose I/O pin. CMOS CVREF O Analog Comparator reference voltage output. AN0 I Analog Analog Input 0. I Analog Ultra Low-Power Wake-up input. ULPWU RA1/AN1/C1INC 30 RA1 I/O ST/ Digital I/O. CMOS AN1 I Analog Analog Input 1. C1INC I Analog Comparator 1 Input C.
PAGE 35
PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Num Pin Type Buffer Type Description PORTB is a bidirectional I/O port. RB0/AN10/FLT0/INT0 13 RB0 I/O ST/ Digital I/O. CMOS AN10 I FLT0 I ST Enhanced PWM Fault input for ECCP1. I ST External Interrupt 0. INT0 RB1/AN8/CTDIN/INT1 Analog Analog Input 10. 14 RB1 I/O AN8 I CTDIN I ST CTMU pulse delay input. INT1 I ST External Interrupt 1. RB2/CANTX/CTED1/ INT2 ST/ Digital I/O.
PAGE 36
PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Num Pin Name RB6/PGC/KBI2 Pin Type Buffer Type Description 22 RB6 I/O PGC I ST In-Circuit Debugger and ICSP™ programming clock input pin. I ST Interrupt-on-change pin. KBI2 RB7/PGD/T3G/KBI3 ST/ Digital I/O. CMOS 23 RB7 I/O PGD I/O ST In-Circuit Debugger and ICSP™ programming data pin. T3G I ST Timer3 external clock gate input. KBI3 I ST Interrupt-on-change pin.
PAGE 37
PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Num Pin Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/SOSCO/SCLKI 48 RC0 I/O ST/ Digital I/O. CMOS SOSCO I ST Timer1 oscillator output. SCLKI I ST Digital SOSC input. RC1/SOSCI 49 RC1 I/O SOSCI RC2/T1G/CCP2 I CMOS SOSC oscillator input. 50 RC2 I/O T1G CCP2 RC3/REFO/SCL/SCK ST/ Digital I/O. CMOS ST/ Digital I/O. CMOS I ST Timer1 external clock gate input.
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PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Num Pin Type Buffer Type Description PORTD is a bidirectional I/O port. RD0/C1INA/PSP0 54 RD0 I/O ST/ Digital I/O. CMOS C1INA I PSP0 I/O ST/ Parallel Slave Port data. CMOS I/O ST/ Digital I/O. CMOS RD1/C1INB/PSP1 Analog Comparator 1 Input A. 55 RD1 C1INB I PSP1 I/O ST/ Parallel Slave Port data. CMOS I/O ST/ Digital I/O. CMOS RD2/C2INA/PSP2 Analog Comparator 1 Input B.
PAGE 39
PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name RD6/P1C/PSP6 Pin Num Pin Type Buffer Type Description 4 RD6 I/O ST/ Digital I/O. CMOS P1C O CMOS Enhanced PWM1 Output C. PSP6 I/O ST/ Parallel Slave Port data. CMOS I/O ST/ Digital I/O. CMOS P1D O CMOS Enhanced PWM1 Output D. PSP7 I/O ST/ Parallel Slave Port data.
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PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Num Pin Type Buffer Type Description PORTE is a bidirectional I/O port. 37 RE0/AN5/RD RE0 I/O AN5 I RD I RE1/AN6/C1OUT/WR ST/ Digital I/O. CMOS Analog Analog Input 5. ST Parallel Slave Port read strobe. 38 RE1 I/O AN6 I Analog Analog Input 6. C1OUT O CMOS Comparator 1 output. WR I RE2/AN7/C2OUT/CS ST/ Digital I/O. CMOS ST Parallel Slave Port write strobe. 39 RE2 I/O ST/ Digital I/O.
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PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Num Pin Type Buffer Type Description PORTF is a bidirectional I/O port. RF0/MDMIN 17 RF0 I/O MDMIN RF1 I MDCIN1 ST Modulator Carrier Input 1. I/O ST/ Digital I/O. CMOS I/O ST/ Digital I/O. CMOS I ST Modulator Carrier Input 2. 45 RF5 I/O ST/ Digital I/O. CMOS I/O ST/ Digital I/O. CMOS O CMOS Modulator output. I/O ST/ Digital I/O. CMOS 52 RF6 MDOUT RF7 ST/ Digital I/O.
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PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Num Pin Type Buffer Type Description PORTG is a bidirectional I/O port. RG0/RX1/DT1 6 RG0 I/O ST/ Digital I/O. CMOS RX1 I ST EUSART asynchronous receive. DT1 I/O ST EUSART synchronous data. (See related TX2/CK2.) RG1/CANTX2 7 RG1 I/O ST/ Digital I/O. CMOS CANTX2 O CMOS CAN bus complimentary transmit output or CAN bus time clock. I/O ST/ Digital I/O.
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PIC18F66K80 FAMILY TABLE 1-6: PIC18F6XK80 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name VSS Pin Num Pin Type 8 Buffer Type Description P VSS Ground reference for logic and I/O pins. VSS 26 P Ground reference for logic and I/O pins. VSS AVSS 42 P 43 P AVSS Ground reference for analog modules. VSS VSS Ground reference for logic and I/O pins. VSS 56 P Ground reference for logic and I/O pins. VSS AVDD 9 P 10 P AVDD Positive supply for analog modules.
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PIC18F66K80 FAMILY NOTES: DS39977F-page 44  2010-2012 Microchip Technology Inc.
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PIC18F66K80 FAMILY 2.0 GUIDELINES FOR GETTING STARTED WITH PIC18FXXKXX MICROCONTROLLERS FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(2) • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • ENVREG (if implemented) and VCAP/VDDCORE pins (see Section 2.
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PIC18F66K80 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
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PIC18F66K80 FAMILY 2.4 Some PIC18FXXKXX families, or some devices within a family, do not provide the option of enabling or disabling the on-chip voltage regulator: Voltage Regulator Pins (ENVREG and VCAP/VDDCORE) The on-chip voltage regulator enable pin, ENVREG, must always be connected directly to either a supply voltage or to ground. Tying ENVREG to VDD enables the regulator, while tying it to ground disables the regulator. Refer to Section 28.
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PIC18F66K80 FAMILY CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the internal voltage regulator of this microcontroller.
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PIC18F66K80 FAMILY 2.6 External Oscillator Pins FIGURE 2-5: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 3.0 “Oscillator Configurations” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins.
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PIC18F66K80 FAMILY NOTES: DS39977F-page 50  2010-2012 Microchip Technology Inc.
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PIC18F66K80 FAMILY 3.0 OSCILLATOR CONFIGURATIONS 3.
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PIC18F66K80 FAMILY TABLE 3-1: HS, EC, XT, LP AND RC MODES: RANGES AND SETTINGS Mode Frequency Range EC1 (low power) FOSC<3:0> Setting 1101 DC-160 kHz (EC1 & EC1IO) EC2 (medium power) 1100 160 kHz-16 MHz 1011 16 MHz-64 MHz 0101 HS1 (medium power) 4 MHz-16 MHz 0011 HS2 (high power) 16 MHz-25 MHz 0010 XT 100 kHz-4 MHz 0001 LP 31.
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PIC18F66K80 FAMILY 3.2 Control Registers The OSCCON register (Register 3-1) controls the main aspects of the device clock’s operation. It selects the oscillator type to be used, which of the power-managed modes to invoke and the output frequency of the INTOSC source. It also provides status on the oscillators. REGISTER 3-1: R/W-0 OSCCON: OSCILLATOR CONTROL REGISTER R/W-1 IDLEN The OSCTUNE register (Register 3-3) controls the tuning and operation of the internal oscillator block.
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PIC18F66K80 FAMILY REGISTER 3-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 2 HFIOFS: HF-INTOSC Frequency Stable bit 1 = HF-INTOSC oscillator frequency is stable 0 = HF-INTOSC oscillator frequency is not stable bit 1-0 SCS<1:0>: System Clock Select bits(4) 1x = Internal oscillator block (LF-INTOSC, MF-INTOSC or HF-INTOSC) 01 = SOSC oscillator 00 = Default primary oscillator (OSC1/OSC2 or HF-INTOSC with or without PLL; defined by the FOSC<3:0> Configuration bits, CONFIG1H<3:0>) Note 1: 2: 3: 4
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PIC18F66K80 FAMILY REGISTER 3-3: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.
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PIC18F66K80 FAMILY 3.3 Clock Sources and Oscillator Switching Essentially, PIC18F66K80 family devices have these independent clock sources: • Primary oscillators • Secondary oscillators • Internal oscillator The primary oscillators can be thought of as the main device oscillators. These are any external oscillators connected to the OSC1 and OSC2 pins, and include the External Crystal and Resonator modes and the External Clock modes.
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PIC18F66K80 FAMILY The use of the flag and control bits in the OSCCON register is discussed in more detail in Section 4.0 “Power-Managed Modes”. Note 1: The Timer1/3/5/7 oscillator must be enabled to select the secondary clock source. The Timerx oscillator is enabled by setting the SOSCEN bit in the Timerx Control register (TxCON<3>). If the Timerx oscillator is not enabled, then any attempt to select a secondary clock source when executing a SLEEP instruction will be ignored.
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PIC18F66K80 FAMILY 3.5 TABLE 3-3: External Oscillator Modes 3.5.1 CRYSTAL OSCILLATOR/CERAMIC RESONATORS (HS MODES) In HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 3-4 shows the pin connections. The oscillator design requires the use of a crystal rated for parallel resonant operation. Note: Use of a crystal rated for series resonant operation may give a frequency out of the crystal manufacturer’s specifications.
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PIC18F66K80 FAMILY EXTERNAL CLOCK INPUT (EC MODES) The EC and ECPLL Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 3-5 shows the pin connections for the EC Oscillator mode.
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PIC18F66K80 FAMILY 3.6 Internal Oscillator Block The PIC18F66K80 family of devices includes an internal oscillator block which generates two different clock signals. Either clock can be used as the microcontroller’s clock source, which may eliminate the need for an external oscillator circuit on the OSC1 and/or OSC2 pins. The Internal oscillator consists of three blocks, depending on the frequency of operation. They are HF-INTOSC, MF-INTOSC and LF-INTOSC.
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PIC18F66K80 FAMILY 3.6.3 INTERNAL OSCILLATOR OUTPUT FREQUENCY AND TUNING The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 16 MHz. It can be adjusted in the user’s application by writing to TUN<5:0> (OSCTUNE<5:0>) in the OSCTUNE register (Register 3-3). When the OSCTUNE register is modified, the INTOSC (HF-INTOSC and MF-INTOSC) frequency will begin shifting to the new frequency. The oscillator will require some time to stabilize.
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PIC18F66K80 FAMILY REGISTER 3-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROON — ROSSLP ROSEL(1) RODIV3 RODIV2 RODIV1 RODIV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ROON: Reference Oscillator Output Enable bit 1 = Reference oscillator output is available on REFO pin 0 = Reference oscillator output is
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PIC18F66K80 FAMILY 3.8 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the SOSC oscillator is operating and providing the device clock.
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PIC18F66K80 FAMILY NOTES: DS39977F-page 64  2010-2012 Microchip Technology Inc.
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PIC18F66K80 FAMILY 4.0 POWER-MANAGED MODES The PIC18F66K80 family of devices offers a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (such as battery-powered devices). There are three categories of power-managed mode: • Run modes • Idle modes • Sleep mode There is an Ultra Low-Power Wake-up (ULPWU) for waking from Sleep mode.
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PIC18F66K80 FAMILY 4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. The HFINTOSC and MF-INTOSC are termed as INTOSC in this chapter. Three bits indicate the current clock source and its status, as shown in Table 4-2.
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PIC18F66K80 FAMILY FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 SOSCI 2 3 n-1 Q3 Q4 Q1 Q2 Q3 n Clock Transition(1) OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC.
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PIC18F66K80 FAMILY If the IRCFx bits and the INTSRC bit are all clear, the INTOSC output (HF-INTOSC/MF-INTOSC) is not enabled and the HFIOFS and MFIOFS bits will remain clear. There will be no indication of the current clock source. The LF-INTOSC source is providing the device clocks. TABLE 4-3: If the IRCFx bits are changed from all clear (thus, enabling the INTOSC output) or if INTSRC or MFIOSEL is set, the HFIOFS or MFIOFS bit is set after the INTOSC output becomes stable. For details, see Table 4-3.
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PIC18F66K80 FAMILY FIGURE 4-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 LF-INTOSC 2 3 n-1 Q3 Q4 Q1 Q2 Q3 n Clock Transition(1) OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC.
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PIC18F66K80 FAMILY 4.3 Sleep Mode 4.4 The power-managed Sleep mode in the PIC18F66K80 family of devices is identical to the legacy Sleep mode offered in all other PIC devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 4-5). All clock source status bits are cleared.
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PIC18F66K80 FAMILY 4.4.1 PRI_IDLE MODE 4.4.2 This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing-sensitive applications, this allows for the fastest resumption of device operation with its more accurate, primary clock source, since the clock source does not have to “warm-up” or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction.
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PIC18F66K80 FAMILY 4.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode provides controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP.
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PIC18F66K80 FAMILY REGISTER 4-1: PMD2: PERIPHERAL MODULE DISABLE REGISTER 2 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — MODMD(1) ECANMD CMP2MD CMP1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 MODMD: Modulator Output Module Disable bit(1) 1 = The modulator output module is disabled; all Modulator Output registers a
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PIC18F66K80 FAMILY REGISTER 4-2: PMD1: PERIPHERAL MODULE DISABLE REGISTER 1 R/W-0 (1) PSPMD R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUMD ADCMD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PSPMD: Peripheral Module Disable bit(1) 1 = The PSP module is disabled; all PSP registers are held in Reset and are not writable 0 =
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PIC18F66K80 FAMILY REGISTER 4-3: PMD0: PERIPHERAL MODULE DISABLE REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSPMD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CCP5MD: CCP5 Module Disable bit 1 = The CCP5 module is disabled; all CCP5 registers are held in Reset and are not writable 0 = The CC
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PIC18F66K80 FAMILY 4.6 Exiting Idle and Sleep Modes An exit from Sleep mode or any of the Idle modes is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power-managed modes. The clocking subsystem actions are discussed in each of the power-managed modes (see Section 4.2 “Run Modes”, Section 4.3 “Sleep Mode” and Section 4.4 “Idle Modes”). 4.6.
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PIC18F66K80 FAMILY 4.7 Ultra Low-Power Wake-up The Ultra Low-Power Wake-up (ULPWU) on pin, RA0, allows a slow falling voltage to generate an interrupt without excess current consumption. To use this feature: 1. 2. 3. 4. 5. A series resistor, between RA0 and the external capacitor, provides overcurrent protection for the RA0/ CVREF/AN0/ULPWU pin and enables software calibration of the time-out (see Figure 4-9).
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PIC18F66K80 FAMILY TABLE 4-4: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Power-Managed Mode Clock Source(5) Exit Delay Clock Ready Status Bits LP, XT, HS HSPLL PRI_IDLE mode EC, RC HF-INTOSC(2) OSTS TCSD(1) HFIOFS MF-INTOSC(2) MFIOFS LF-INTOSC SEC_IDLE mode SOSC None TCSD(1) SOSCRUN TCSD(1) MFIOFS HF-INTOSC(2) RC_IDLE mode MF-INTOSC(2) HFIOFS LF-INTOSC Sleep mode TOST(3) HSPLL TOST + trc(3) EC, RC TCSD(1) HF-INTOSC(2) MF-INTOSC(2) LF-INTOSC
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PIC18F66K80 FAMILY 5.
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PIC18F66K80 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1(1) R/W-1 R/W-1 R-1 R-1 R/W-0(2) R/W-0 IPEN SBOREN CM RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enables priority levels on interrupts 0 = Disables priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: B
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PIC18F66K80 FAMILY 5.2 Master Clear Reset (MCLR) The MCLR pin provides a method for triggering an external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. FIGURE 5-2: In PIC18F66K80 family devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 11.6 “PORTE, TRISE and LATE Registers” for more information.
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PIC18F66K80 FAMILY 5.4 Brown-out Reset (BOR) The PIC18F66K80 family has four BOR Power modes: • • • • High-Power BOR Medium Power BOR Low-Power BOR Zero-Power BOR Each power mode is selected by the BORPWR<1:0> setting (CONFIG2L<6:5>). For low, medium and high-power BOR, the module monitors the VDD depending on the BORV<1:0> setting (CONFIG1L<3:2>). The typical current draw (IBOR) for zero, low and medium power BOR is 200 nA, 750 nA and 3 A, respectively. A BOR event re-arms the Power-on Reset.
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PIC18F66K80 FAMILY 5.5 Configuration Mismatch (CM) The Configuration Mismatch (CM) Reset is designed to detect, and attempt to recover from, random memory corrupting events. These include Electrostatic Discharge (ESD) events, which can cause widespread, single bit changes throughout the device and result in catastrophic failure.
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PIC18F66K80 FAMILY 5.6.2 OSCILLATOR START-UP TIMER (OST) 5.6.4 On power-up, the time-out sequence is as follows: The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (Parameter 33). This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP, HS and HSPLL modes and only on Power-on Reset or on exit from most power-managed modes. 5.6.
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PIC18F66K80 FAMILY FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 5-5: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET  2010-2012 Microchip Technology
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PIC18F66K80 FAMILY FIGURE 5-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT TOST TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL  2 ms max. First three stages of the PWRT timer. DS39977F-page 86  2010-2012 Microchip Technology Inc.
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PIC18F66K80 FAMILY 5.7 different Reset situations, as indicated in Table 5-3. These bits are used in software to determine the nature of the Reset. Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on a Power-on Reset and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Table 5-4 describes the Reset states for all of the Special Function Registers.
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PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt TOSU PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu(3) TOSL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu(3) STKPTR PIC18F2XK80 PIC18F4XK80 PIC18F6XK80
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PIC18F66K80 FAMILY TABLE 5-4: Register POSTINC2 INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt N/A N/A N/A POSTDEC2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A PREINC2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A PLUSW2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 N/A N/A N/A FSR2H PIC18F2XK80 PIC
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PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt BAUDCON2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 01x0 0-00 01x0 0-00 uuuu u-uu IPR4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 -111 1111 -111 uuuu -uuu PIR4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 -000 0000 -000 uuuu -uuu PIE4 PIC18F2XK80 PIC18F4XK80 PIC18F
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PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt CCPTMRS PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---0 0000 ---x xxxx ---u uuuu TRISG PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---1 1111 ---1 1111 ---u uuuu TRISF PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1111 1111 1111 1111 uuuu uuuu TRISE PIC18F2XK80 PIC18F4XK80 PIC1
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PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu Applicable Devices PIE5 PIC18F2XK80 PIC18F4XK80 EEADRH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---- --00 ---- --00 ---- --00 EEADR PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0000 0000 0000 uuuu uuuu EEDATA PIC18F2XK80 PIC18F4XK80 PIC18
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PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt 0000 0000 0000 0000 uuuu uuuu PMD1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 PMD2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 ---- 0000 ---- 0000 ---- uuuu PADCFG1 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 ---0 0000 ---0 uuuu ---u CTMUCONH PIC18F2XK80 PIC18F4XK80 PIC
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PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt RXB1EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB1EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXB1SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx x-xx uuuu u-uu uuuu u-uu RXB1SIDH PIC18F2XK80 PIC18F4
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PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu Applicable Devices TXB1SIDH PIC18F2XK80 PIC18F4XK80 TXB1CON PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 0000 0-00 0000 0-00 uuuu u-uu CANCON_RO3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 1000 0000 1000 0000 uuuu uuuu CANSTAT_RO3 PIC18F2XK80 PIC
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PIC18F66K80 FAMILY TABLE 5-4: Register RXF3EIDH INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu Applicable Devices PIC18F2XK80 PIC18F4XK80 RXF3SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxx- x-xx uuu- u-uu uuu- u-uu RXF3SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF2EIDL PIC18F2XK80 PIC18F4
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PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt B4D5 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B4D4 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B4D3 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B4D2 PIC18F2XK80 PIC18F4XK80 PIC18F6XK8
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PIC18F66K80 FAMILY TABLE 5-4: Register B2D1 INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu Applicable Devices PIC18F2XK80 PIC18F4XK80 B2D0 PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B2DLC PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 -xxx xxxx -uuu uuuu -uuu uuuu B2EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6
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PIC18F66K80 FAMILY TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt B0EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B0SIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx x-xx uuuu u-uu uuuu u-uu B0SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu B0CON PIC18F2XK80 PIC18F4XK80 PIC
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PIC18F66K80 FAMILY TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt RXF12SIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF11EIDL PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF11EIDH PIC18F2XK80 PIC18F4XK80 PIC18F6XK80 xxxx xxxx uuuu uuuu uuuu uuuu RXF11SIDL PIC18F2XK80 P
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PIC18F66K80 FAMILY 6.0 MEMORY ORGANIZATION PIC18F66K80 family devices have these types of memory: • Program Memory • Data RAM • Data EEPROM As Harvard architecture devices, the data and program memories use separate busses. This enables concurrent access of the two memory spaces. FIGURE 6-1: The data EEPROM, for practical purposes, can be regarded as a peripheral device because it is addressed and accessed through a set of control registers.
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PIC18F66K80 FAMILY 6.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit Program Counter (PC) that is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction). The entire PIC18F66K80 family offers a range of on-chip Flash program memory sizes, from 32 Kbytes (16,384 single-word instructions) to 64 Kbytes (32,768 single-word instructions).
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PIC18F66K80 FAMILY 6.1.2 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits and is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU.
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PIC18F66K80 FAMILY 6.1.3.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 6-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off of the stack. On Reset, the Stack Pointer value will be zero.
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PIC18F66K80 FAMILY 6.1.3.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit (CONFIG4L<0>). When STVREN is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device Reset.
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PIC18F66K80 FAMILY 6.2 6.2.2 PIC18 Instruction Cycle 6.2.1 An “Instruction Cycle” consists of four Q cycles, Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction (such as GOTO) causes the Program Counter to change, two cycles are required to complete the instruction.
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PIC18F66K80 FAMILY 6.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as two or four bytes in program memory. The Least Significant Byte (LSB) of an instruction word is always stored in a program memory location with an even address (LSB = 0). To maintain alignment with instruction boundaries, the PC increments in steps of two and the LSB will always read ‘0’ (see Section 6.1.2 “Program Counter”).
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PIC18F66K80 FAMILY 6.3 Note: Data Memory Organization The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 6.6 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4,096 bytes of data memory. The memory space is divided into 16 banks that contain 256 bytes each.
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PIC18F66K80 FAMILY FIGURE 6-6: DATA MEMORY MAP FOR PIC18FX5K80 AND PIC18FX6K80 DEVICES BSR<3:0> Data Memory Map 00h = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 Note 1: Bank 0 FFh 00h Bank 1 Access RAM GPR GPR 1FFh 200h FFh 00h Bank 2 GPR FFh 00h Bank 3 2FFh 300h GPR FFh 00h Bank 4 When a = 1: 3FFh 400h The BSR specifies the bank used by the instruction.
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PIC18F66K80 FAMILY FIGURE 6-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 7 0 0 0 0 0 0 0 Bank Select(2) 1 0 000h Data Memory Bank 0 100h Bank 1 200h 300h Bank 2 00h 7 FFh 00h 1 From Opcode(2) 1 11 1 11 1 0 11 11 FFh 00h FFh 00h Bank 3 through Bank 13 E00h Bank 14 F00h FFFh Note 1: 2: 6.3.2 Bank 15 FFh 00h FFh 00h FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank.
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PIC18F66K80 FAMILY 6.3.4 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy all of Bank 15 (F00h to FFFh) and the top part of Bank 14 (EF4h to EFFh). A list of these registers is given in Table 6-1 and Table 6-2. TABLE 6-1: FFFh TOSU FFEh TOSH FFDh Addr.
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PIC18F66K80 FAMILY TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F66K80 FAMILY (CONTINUED) Name Addr. Addr. F3Fh CANCON_RO0(5) F3Eh CANSTAT_RO0(5) Name Addr. Name F0Fh CANCON_RO3(5) EDFh CANCON_RO4(5) Name Addr. EAFh CANCON_RO7(5) Name Addr.
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PIC18F66K80 FAMILY TABLE 6-2: Addr.
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PIC18F66K80 FAMILY TABLE 6-2: Addr.
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PIC18F66K80 FAMILY TABLE 6-2: Addr.
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PIC18F66K80 FAMILY TABLE 6-2: Addr.
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PIC18F66K80 FAMILY TABLE 6-2: Addr.
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PIC18F66K80 FAMILY TABLE 6-2: Addr.
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PIC18F66K80 FAMILY TABLE 6-2: Addr.
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PIC18F66K80 FAMILY TABLE 6-2: Addr.
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PIC18F66K80 FAMILY TABLE 6-2: Addr.
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PIC18F66K80 FAMILY 6.3.5 STATUS REGISTER The STATUS register, shown in Register 6-2, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the write to these five bits is disabled. These bits are set or cleared according to the device logic.
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PIC18F66K80 FAMILY 6.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. For more information, see Section 6.6 “Data Memory and the Extended Instruction Set”. While the program memory can be addressed in only one way, through the Program Counter, information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed.
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PIC18F66K80 FAMILY 6.4.3.1 FSR Registers and the INDF Operand mapped in the SFR space, but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers: FSRnH and FSRnL.
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PIC18F66K80 FAMILY 6.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value.
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PIC18F66K80 FAMILY 6.6 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Using the Access Bank for many of the core PIC18 instructions introduces a new addressing mode for the data memory space. This mode also alters the behavior of Indirect Addressing using FSR2 and its associated operands.
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PIC18F66K80 FAMILY FIGURE 6-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When a = 0 and f  60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and FFFh. This is the same as locations, F60h to FFFh, (Bank 15) of data memory. Locations below 060h are not available in this addressing mode.
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PIC18F66K80 FAMILY 6.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user-defined “window” that can be located anywhere in the data memory space.
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PIC18F66K80 FAMILY 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 64 bytes at a time.
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PIC18F66K80 FAMILY FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: The Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 “Writing to Flash Program Memory”. 7.
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PIC18F66K80 FAMILY REGISTER 7-1: EECON1: EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Accesses Flash program memory 0 = Accesses data EEPROM memory bit 6 CFGS: Flash Prog
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PIC18F66K80 FAMILY 7.2.2 TABLAT – TABLE LATCH REGISTER 7.2.4 The Table Latch (TABLAT) is an eight-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 7.2.3 TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT.
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PIC18F66K80 FAMILY 7.3 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. Reading the Flash Program Memory The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. FIGURE 7-4: The internal program memory is typically organized by words.
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PIC18F66K80 FAMILY 7.4 Erasing Flash Program Memory The erase blocks are 32 words or 64 bytes. Word erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. The TBLPTR<5:0> bits are ignored. The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the Flash program memory.
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PIC18F66K80 FAMILY 7.5 The EEPROM on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. Writing to Flash Program Memory The programming blocks are 32 words or 64 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 64 holding registers for programming by the table writes.
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PIC18F66K80 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF SIZE_OF_BLOCK COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; number of bytes in erase block TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0
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PIC18F66K80 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY Required Sequence 7.5.
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PIC18F66K80 FAMILY NOTES: DS39977F-page 138  2010-2012 Microchip Technology Inc.
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PIC18F66K80 FAMILY 8.0 DATA EEPROM MEMORY The data EEPROM is a nonvolatile memory array, separate from the data RAM and program memory, that is used for long-term storage of program data. It is not directly mapped in either the register file or program memory space, but is indirectly addressed through the Special Function Registers (SFRs). The EEPROM is readable and writable during normal operation over the entire VDD range.
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PIC18F66K80 FAMILY REGISTER 8-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Accesses Flash program memory 0 = Accesses data EEPROM memory bit 6 CFGS: Flash
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PIC18F66K80 FAMILY 8.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADRH:EEADR register pair, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available after one instruction cycle, in the EEDATA register. It can be read after one NOP instruction. EEDATA will hold this value until another read operation or until it is written to by the user (during a write operation).
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PIC18F66K80 FAMILY EXAMPLE 8-1: MOVLW MOVWF MOVLW MOVWF BCF BCF BSF NOP MOVF EXAMPLE 8-2: Required Sequence DS39977F-page 142 DATA EEPROM READ DATA_EE_ADDRH EEADRH DATA_EE_ADDR EEADR EECON1, EEPGD EECON1, CFGS EECON1, RD ; ; ; ; ; ; ; EEDATA, W ; W = EEDATA Upper bits of Data Memory Address to read Lower bits of Data Memory Address to read Point to DATA memory Access EEPROM EEPROM Read DATA EEPROM WRITE MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BCF BCF BSF DATA_EE_ADDRH EEADRH DATA_EE_ADDR EEADR DATA_EE
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PIC18F66K80 FAMILY 8.6 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal data EEPROM regardless of the state of the code-protect Configuration bit. Refer to Section 28.0 “Special Features of the CPU” for additional information. 8.
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PIC18F66K80 FAMILY TABLE 8-1: Name REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF EEADRH EEPROM Address Register High Byte EEADR EEPROM Address Register Low Byte EEDATA EEPROM Data Register EECON2 EEPROM Control Register 2 (not a physical register) EECON1 EEPGD CFGS — FREE WRERR WREN WR RD IPR4 TMR4IP EEIP CMP2IP CMP1IP — CCP5IP CCP4IP CCP3IP PIR4 TMR4IF
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PIC18F66K80 FAMILY 9.0 8 x 8 HARDWARE MULTIPLIER 9.1 Introduction EXAMPLE 9-1: MOVF MULWF All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register.
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PIC18F66K80 FAMILY Example 9-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0).
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PIC18F66K80 FAMILY 10.0 INTERRUPTS Members of the PIC18F66K80 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress.
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PIC18F66K80 FAMILY FIGURE 10-1: PIC18F66K80 FAMILY INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7,5:0> PIE2<7,5:0> IPR2<7,5:0> PIR3<7,5> PIE3<7,5> IPR3<7,5> PIR4<7:0> PIE4<7:0> IPR4<7:0> PIR5<7:0> PIE5<7:0> IPR5<7:0> Wake-up if in Idle or Sleep modes TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP Interrupt to CPU Vector to Location 0008h GIE/GIEH IPEN IPEN PEIE/GIEL IPEN High-Priority Interrupt Generation Low-Priority Interrupt G
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PIC18F66K80 FAMILY 10.1 INTCON Registers Note: The INTCON registers are readable and writable registers that contain various enable, priority and flag bits. REGISTER 10-1: R/W-0 INTCON: INTERRUPT CONTROL REGISTER R/W-0 GIE/GIEH Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
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PIC18F66K80 FAMILY REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port TRIS values bit 6 INTEDG0: External In
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PIC18F66K80 FAMILY REGISTER 10-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Lo
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PIC18F66K80 FAMILY 10.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are six Peripheral Interrupt Request (Flag) registers (PIR1 through PIR5). Note 1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>).
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PIC18F66K80 FAMILY REGISTER 10-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF — — — BCLIF HLVDIF TMR3IF TMR3GIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (bit must be cleared in software) 0
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PIC18F66K80 FAMILY REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 U-0 R-0 R-0 R/W-0 R/W-0 R/W-0 U-0 — — RC2IF TX2IF CTMUIF CCP2IF CCP1IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IF: EUSARTx Receive Interrupt Flag bit 1 = The EUSARTx receive buffer, RCREG2, is full (cleared when RCREG2 i
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PIC18F66K80 FAMILY REGISTER 10-7: PIR4: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 4 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 TMR4IF EEIF CMP2IF CMP1IF — CCP5IF CCP4IF CCP3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR4IF: TMR4 Overflow Interrupt Flag bit 1 = TMR4 register overflowed (must be cleared in software) 0 = TMR4 register did not overflow bit 6 EEIF: Da
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PIC18F66K80 FAMILY REGISTER 10-8: PIR5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 5 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIF WAKIF ERRIF TXB2IF TXB1IF TXB0IF RXB1IF RXB0IF/ FIFOFIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRXIF: Invalid Message Received Interrupt Flag bits 1 = An invalid message occurred on the CAN bus 0 = No invalid me
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PIC18F66K80 FAMILY 10.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are six Peripheral Interrupt Enable registers (PIE1 through PIE6). When IPEN (RCON<7>) = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
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PIC18F66K80 FAMILY REGISTER 10-10: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE — — — BCLIE HLVDIE TMR3IE TMR3GIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6-4 Unimplemented: Read as ‘0’ bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 =
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PIC18F66K80 FAMILY REGISTER 10-11: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 U-0 R-0 R-0 R/W-0 R/W-0 R/W-0 U-0 — — RC2IE TX2IE CTMUIE CCP2IE CCP1IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IE: EUSARTx Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TX2IE: EUSARTx Transmit Interrupt Enable bit 1 = Enabled 0 = Dis
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PIC18F66K80 FAMILY REGISTER 10-12: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 TMR4IE EEIE CMP2IE CMP1IE — CCP5IE CCP4IE CCP3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR4IE: TMR4 Overflow Interrupt Flag bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 EEIE: Data EEDATA/Flash Write Operation Interrupt Flag bit 1
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PIC18F66K80 FAMILY REGISTER 10-13: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRXIE WAKIE ERRIE TXB2IE TXB1IE TXB0IE RXB1IE RXB0IE/ FIFOFIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRXIE: Invalid Message Received Interrupt Flag bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 WAKIE: Bus Wake
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PIC18F66K80 FAMILY 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are six Peripheral Interrupt Priority registers (IPR1 through IPR6). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit (RCON<7>) be set.
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PIC18F66K80 FAMILY REGISTER 10-15: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP — — — BCLIP HLVDIP TMR3IP TMR3GIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6-4 Unimplemented: Read as ‘0’ bit 3 BCLIP: Bus Collision Interrupt Priority bit
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PIC18F66K80 FAMILY REGISTER 10-16: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 — — RC2IP TX2IP CTMUIP CCP2IP CCP1IP — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IP: EUSARTx Receive Priority Flag bit 1 = High priority 0 = Low priority bit 4 TX2IP: EUSARTx Transmit Interrupt Priority bit 1 =
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PIC18F66K80 FAMILY REGISTER 10-17: IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4 R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 TMR4IP EEIP CMP2IP CMP1IP — CCP5IP CCP4IP CCP3IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR4IP: TMR4 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 EEIP: EE Interrupt Priority bit 1 = High priority 0 = Low priority bi
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PIC18F66K80 FAMILY REGISTER 10-18: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP TXB2IP TXB1IP TXB0IP RXB1IP RXB0IP/ FIFOFIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 IRXIP: Invalid Message Received Interrupt Priority bits 1 = High priority 0 = Low priority bit 6 WAKIP: Bus Wake-up Activity Interrupt Priori
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PIC18F66K80 FAMILY 10.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN).
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PIC18F66K80 FAMILY 10.6 INTx Pin Interrupts 10.7 External interrupts on the RB0/INT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge. If that bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE.
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PIC18F66K80 FAMILY 10.9 If a fast return from interrupt is not used (see Section 6.3 “Data Memory Organization”), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine (ISR). Depending on the user’s application, other registers also may need to be saved. Context Saving During Interrupts During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the Fast Return Stack.
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PIC18F66K80 FAMILY NOTES: DS39977F-page 170  2010-2012 Microchip Technology Inc.
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PIC18F66K80 FAMILY 11.0 I/O PORTS 11.1 Depending on the device selected and features enabled, there are up to seven ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.
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PIC18F66K80 FAMILY REGISTER 11-1: R/W-0 PADCFG1: PAD CONFIGURATION REGISTER R/W-0 RDPU(1) REPU (1) R/W-0 (2) RFPU R/W-0 RGPU (2) U-0 U-0 U-0 R/W-0 — — — CTMUDS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RDPU: PORTD Pull-up Enable bit(1) 1 = PORTD pull-up resistors are enabled by individual port latch values 0 = All PORTD pull-up resistors are disabled bi
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PIC18F66K80 FAMILY 11.1.3 OPEN-DRAIN OUTPUTS FIGURE 11-2: The output pins for several peripherals are also equipped with a configurable, open-drain output option. This allows the peripherals to communicate with external digital logic, operating at a higher voltage level, without the use of level translators. USING THE OPEN-DRAIN OUTPUT (USARTx SHOWN AS EXAMPLE) 3.
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PIC18F66K80 FAMILY 11.1.4 ANALOG AND DIGITAL PORTS 11.1.5 Many of the ports multiplex analog and digital functionality, providing a lot of flexibility for hardware designers. PIC18F66K80 family devices can make any analog pin analog or digital, depending on an application’s needs. The ports’ analog/digital functionality is controlled by the registers: ANCON0 and ANCON1.
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PIC18F66K80 FAMILY 11.2 PORTA, TRISA and LATA Registers PORTA is a seven-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISA and LATA. RA5 and RA<3:0> are multiplexed with analog inputs for the A/D Converter. The operation of the analog inputs as A/D Converter inputs is selected by clearing or setting the ANSELx control bits in the ANCON1 register.
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PIC18F66K80 FAMILY TABLE 11-1: PORTA FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RA0 0 O DIG LATA<0> data output; not affected by analog input. 1 I ST PORTA<0> data input; disabled when analog input is enabled. CVREF x O ANA Comparator voltage reference output. Enabling this feature disables digital I/O. AN0 1 I ANA A/D Input Channel 0. Default input configuration on POR; does not affect digital output.
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PIC18F66K80 FAMILY 11.3 PORTB, TRISB and LATB Registers PORTB is an eight-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISB and LATB. All pins on PORTB are digital only.
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PIC18F66K80 FAMILY TABLE 11-3: PORTB FUNCTIONS Pin Name RB0/AN10/C1INA FLT0/INT0 RB1/AN8/C1INB/ P1B/CTDIN/INT1 RB2/CANTX/C1OUT/ P1C/CTED1/INT2 RB3/CANRX/ C2OUT/P1D/ CTED2/INT3 Legend: Note 1: 2: 3: 4: Function TRIS Setting I/O I/O Type RB0 0 O DIG 1 I ST PORTB<0> data input; weak pull-up when RBPU bit is cleared. AN10 1 I ANA A/D Input Channel 10 and Comparator C1+ input. Default input configuration on POR. C1INA(1) 1 I ANA Comparator 1 Input A.
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PIC18F66K80 FAMILY TABLE 11-3: PORTB FUNCTIONS (CONTINUED) Pin Name Function TRIS Setting I/O I/O Type RB4/AN9/C2INA/ ECCP1/P1A/CTPLS/ KBI0 RB4 0 O DIG 1 I ST AN9 1 I ANA A/D Input Channel 9 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. C2INA(1) 2 I ANA Comparator 2 Input A. ECCP1(1) 0 O DIG ECCP1 compare output and ECCP1 PWM output. Takes priority over port data. 1 I ST ECCP1 capture input.
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PIC18F66K80 FAMILY TABLE 11-4: Name PORTB LATB TRISB SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT
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PIC18F66K80 FAMILY 11.4 PORTC, TRISC and LATC Registers PORTC is an eight-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISC and LATC. Only PORTC pins, RC2 through RC7, are digital only pins. PORTC is multiplexed with CCP, MSSP and EUSARTx peripheral functions (Table 11-5). The pins have Schmitt Trigger input buffers. The pins for CCP, SPI and EUSARTx are also configurable for open-drain output whenever these functions are active.
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PIC18F66K80 FAMILY TABLE 11-5: Pin Name RC0/SOSCO/ SCLKI RC1/SOSCI RC2/T1G/ CCP2 RC3/REFO/ SCL/SCK PORTC FUNCTIONS Function TRIS Setting I/O I/O Type RC0 0 O DIG LATC<0> data output. 1 I ST PORTC<0> data input. SOSCO 1 I ST SOSC oscillator output. SCLKI 1 I ST Digital clock input; enabled when SOSC oscillator is disabled. RC1 0 O DIG LATC<1> data output. 1 I ST PORTC<1> data input. SOSCI x I ANA SOSC oscillator input. RC2 0 O DIG LATC<2> data output.
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PIC18F66K80 FAMILY TABLE 11-5: Pin Name RC7/CANRX/ RX1/DT1/ CCP4 PORTC FUNCTIONS (CONTINUED) Function TRIS Setting I/O I/O Type RC7 0 O DIG LATC<7> data output. 1 I ST PORTC<7> data input. CANRX(2) 1 I ST CAN bus RX. RX1(1) 1 I ST Asynchronous serial receive data input (EUSARTx module). DT1(1) 1 O DIG Synchronous serial data output (EUSARTx module); takes priority over port data. 1 I ST Synchronous serial data input (EUSARTx module); user must configure as an input.
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PIC18F66K80 FAMILY 11.5 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISD and LATD. Note: RD3 has a CTMU functionality. PORTD is unavailable on 28-pin devices. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output.
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PIC18F66K80 FAMILY TABLE 11-7: Pin Name RD0/C1INA/ PSP0 RD1/C1INB/ PSP1 RD2/C2INA/ PSP2 RD3/C2INB/ CTMUI/PSP3 RD4/ECCP1/ P1A/PSP4 PORTD FUNCTIONS Function TRIS Setting I/O I/O Type RD0 0 O DIG 1 I ST PORTD<0> data input. C1INA 1 I ANA Comparator 1 Input A. PSP0 x I/O ST Parallel Slave Port data. (1) 0 O DIG LATD<1> data output. 1 I ST PORTD<1> data input. C1INB(1) 1 I ANA Comparator 1 Input B. PSP1(1) x I/O ST Parallel Slave Port data.
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PIC18F66K80 FAMILY TABLE 11-7: Pin Name PORTD FUNCTIONS (CONTINUED) Function TRIS Setting I/O I/O Type RD7 0 O DIG LATD<7> data output. 1 I ST PORTD<7> data input. RX2(1) 1 I ST Asynchronous serial receive data input (EUSARTx module). DT2(1) 1 O DIG Synchronous serial data output (EUSARTx module); takes priority over port data. 1 I ST Synchronous serial data input (EUSARTx module); user must configure as an input. P1D 0 O DIG ECCP1 Enhanced PWM output, Channel D.
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PIC18F66K80 FAMILY 11.6 weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on any device Reset. PORTE, TRISE and LATE Registers PORTE is a seven-bit-wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISE and LATE. Note: PORTE is unavailable on 28-pin devices. All pins on PORTE are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output.
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PIC18F66K80 FAMILY TABLE 11-9: Pin Name PORTE FUNCTIONS (CONTINUED) Function TRIS Setting I/O I/O Type RE5(1) 0 O DIG 1 I ST PORTE<5> data input. CANTX(1,2) 0 O DIG CAN bus TX. RE6(1) 0 O DIG LATE<6> data output. 1 I ST PORTE<6> data input. RX2(1) 1 I ST Asynchronous serial receive data input (EUSARTx module). DT2(1) 1 O DIG Synchronous serial data output (EUSARTx module); takes priority over port data.
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PIC18F66K80 FAMILY 11.7 PORTF, LATF and TRISF Registers On device Resets, pins, RF<7:1>, are configured as analog inputs and are read as ‘0’. Note: PORTF is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISF and LATF. All pins on PORTF are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output.
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PIC18F66K80 FAMILY 11.8 PORTG, TRISG and LATG Registers PORTG is a 5-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISG and LATG. Note: PORTG is only available on 64-pin devices. PORTG is multiplexed with EUSARTx and CCP, ECCP, Analog, Comparator and Timer input functions (Table 11-13). When operating as I/O, all PORTG pins have Schmitt Trigger input buffers. The open-drain functionality for the EUARTx can be configured using ODCON.
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PIC18F66K80 FAMILY TABLE 11-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTG — — — RG4 RG3 RG2 RG1 RG0 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 — — — CTMUDS PADCFG1 RDPU REPU (1) RFPU (1) RGPU Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG. Note 1: These bits are unimplemented on 28-pin devices; read as ‘0’.  2010-2012 Microchip Technology Inc.
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PIC18F66K80 FAMILY 11.9 Parallel Slave Port PORTD can function as an 8-bit-wide Parallel Slave Port (PSP), or microprocessor port, when control bit, PSPMODE (PSPCON<4>), is set. The port is asynchronously readable and writable by the external world through the RD control input pin (RE0/AN5/RD) and WR control input pin (RE1/AN6/C1OUT/WR). Note: The Parallel Slave Port is available only on 40/44-pin and 64-pin devices. The PSP can directly interface to an 8-bit microprocessor data bus.
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PIC18F66K80 FAMILY REGISTER 11-5: PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IBF OBF IBOV PSPMODE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status
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PIC18F66K80 FAMILY FIGURE 11-5: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 11-15: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 LATE LATE7
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PIC18F66K80 FAMILY 12.0 Note: DATA SIGNAL MODULATOR The Data Signal Modulator is only available on 64-pin devices (PIC18F6XK80). The Data Signal Modulator (DSM) is a peripheral which allows the user to mix a data stream, also known as a modulator signal, with a carrier signal to produce a modulated output. Both the carrier and the modulator signals are supplied to the DSM module, either internally from the output of a peripheral, or externally through an input pin.
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PIC18F66K80 FAMILY FIGURE 12-1: SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR MDCH<3:0> VSS MDCIN1 MDCIN2 REFO Clock ECCP1 CCP2 CCP3 CCP4 CCP5 Reserved No Channel Selected MDEN 0000 0001 0010 0011 0100 0101 CARH 0110 0111 1000 1001 ** 1111 EN Data Signal Modulator MDCHPOL D SYNC MDMS<3:0> MDBIT MDMIN MSSP (SDO) EUSART1 (TX) EUSART2 (TX) ECCP1 CCP2 CCP3 CCP4 CCP5 Reserved No Channel Selected Q 0000 0001 0010 0011 0100 0101 0110 MOD 0111 1000 1001 1 0 MDCHSYNC MDOUT MDOPOL 1010 MDOE * * 1
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PIC18F66K80 FAMILY 12.1 DSM Operation The DSM module can be enabled by setting the MDEN bit in the MDCON register. Clearing the MDEN bit in the MDCON register, disables the DSM module by automatically switching the carrier high and carrier low signals to the VSS signal source. The modulator signal source is also switched to the MDBIT in the MDCON register. This not only assures that the DSM module is inactive, but that it is also consuming the least amount of current.
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PIC18F66K80 FAMILY FIGURE 12-2: ON/OFF KEYING (OOK) SYNCHRONIZATION Carrier Low (CARL) Carrier High (CARH) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 MDCHSYNC = 1 MDCLSYNC = 1 MDCHSYNC = 0 MDCLSYNC = 0 MDCHSYNC = 0 MDCLSYNC = 1 EXAMPLE 12-1: NO SYNCHRONIZATION (MDCHSYNC = 0, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 0 Active Carrier State FIGURE 12-3: CARH CARL CARH CARL CARRIER HIGH SYNCHRONIZATION (MDCHSYNC = 1, MDCLSYNC = 0) Carrier High (CARH
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PIC18F66K80 FAMILY FIGURE 12-4: CARRIER LOW SYNCHRONIZATION (MDCHSYNC = 0, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 1 Active Carrier State FIGURE 12-5: CARH CARL CARH CARL FULL SYNCHRONIZATION (MDCHSYNC = 1, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) Falling Edges Used to Sync MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier State CARH  2010-2012 Microchip Technology Inc.
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PIC18F66K80 FAMILY 12.5 Carrier Source Polarity Select The signal provided from any selected input source for the carrier high and carrier low signals can be inverted. Inverting the signal for the carrier high source is enabled by setting the MDCHPOL bit of the MDCARH register. Inverting the signal for the carrier low source is enabled by setting the MDCLPOL bit of the MDCARL register. 12.
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PIC18F66K80 FAMILY REGISTER 12-1: MDCON: MODULATION CONTROL REGISTER R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 U-0 U-0 R/W-0 MDEN MDOE MDSLR MDOPOL MDO — — MDBIT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDEN: Modulator Module Enable bit 1 = Modulator module is enabled and mixing input signals 0 = Modulator module is disabled and has no output bit 6 MDOE: Modulator Module Pin Output
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PIC18F66K80 FAMILY REGISTER 12-2: MDSRC: MODULATION SOURCE CONTROL REGISTER R/W-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x MDSODIS — — — MDSRC3 MDSRC2 MDSRC1 MDSRC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MDSODIS: Modulation Source Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDMS<3:0>) is disabled 0 = Output signal d
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PIC18F66K80 FAMILY REGISTER 12-3: MDCARH: MODULATION HIGH CARRIER CONTROL REGISTER R/W-0 R/W-x R/W-x U-0 R/W-x R/W-x R/W-x R/W-x MDCHODIS MDCHPOL MDCHSYNC — MDCH3(1) MDCH2(1) MDCH1(1) MDCH0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MDCHODIS: Modulator High Carrier Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDC
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PIC18F66K80 FAMILY REGISTER 12-4: MDCARL: MODULATION LOW CARRIER CONTROL REGISTER R/W-0 R/W-x R/W-x U-0 R/W-x R/W-x R/W-x R/W-x MDCLODIS MDCLPOL MDCLSYNC — MDCL3(1) MDCL2(1) MDCL1(1) MDCL0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MDCLODIS: Modulator Low Carrier Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDCL<
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PIC18F66K80 FAMILY 13.0 TIMER0 MODULE The Timer0 module incorporates the following features: • Software selectable operation as a timer or counter in both 8-bit or 16-bit modes • Readable and writable registers • Dedicated 8-bit, software programmable prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 13-1: The T0CON register (Register 13-1) controls all aspects of the module’s operation, including the prescale selection.
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PIC18F66K80 FAMILY 13.1 Timer0 Operation Timer0 can operate as either a timer or a counter. The mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 13.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.
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PIC18F66K80 FAMILY 13.3 13.3.1 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable. Its value is set by the PSA and T0PS<2:0> bits (T0CON<3:0>), which determine the prescaler assignment and prescale ratio. The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution. 13.4 Clearing the PSA bit assigns the prescaler to the Timer0 module.
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PIC18F66K80 FAMILY NOTES: DS39977F-page 208  2010-2012 Microchip Technology Inc.
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PIC18F66K80 FAMILY 14.0 TIMER1 MODULE The Timer1 timer/counter module incorporates these features: • Software selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR1H and TMR1L) • Selectable clock source (internal or external) with device clock or SOSC oscillator internal options • Interrupt-on-overflow • Reset on ECCP Special Event Trigger • Timer with gated control Figure 14-1 displays a simplified block diagram of the Timer1 module.
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PIC18F66K80 FAMILY REGISTER 14-1: T1CON: TIMER1 CONTROL REGISTER (CONTINUED) bit 1 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare features. DS39977F-page 210  2010-2012 Microchip Technology Inc.
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PIC18F66K80 FAMILY 14.1 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), displayed in Register 14-2, is used to control the Timer1 gate.
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PIC18F66K80 FAMILY 14.2 14.3.2 Timer1 Operation The Timer1 module is an 8 or 16-bit incrementing counter that is accessed through the TMR1H:TMR1L register pair. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter. It increments on every selected edge of the external source.
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PIC18F66K80 FAMILY FIGURE 14-1: TIMER1 BLOCK DIAGRAM T1GSS<1:0> T1G T1GSPM 00 From TMR2 Match PR2 01 From Comparator 1 Output 10 0 T1G_IN T1GVAL 0 From Comparator 2 Output Single Pulse D Q CK R Q 11 TMR1ON T1GPOL 1 Acq.
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PIC18F66K80 FAMILY 14.4 Timer1 16-Bit Read/Write Mode FIGURE 14-2: Timer1 can be configured for 16-bit reads and writes. When the RD16 control bit (T1CON<1>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L loads the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register.
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PIC18F66K80 FAMILY For more details on selecting the optimum C1 and C2 for a given crystal, see the crystal manufacture’s applications information. The optimum value depends in part on the amount of parasitic capacitance in the circuit, which is often unknown. For that reason, it is highly recommended that thorough testing and validation of the oscillator be performed after values have been selected. 14.5.
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PIC18F66K80 FAMILY 14.7 Resetting Timer1 Using the ECCP Special Event Trigger If ECCP modules are configured to use Timer1 and to generate a Special Event Trigger in Compare mode (CCP1M<3:0> = 1011), this signal will reset Timer1. The trigger from ECCP will also start an A/D conversion if the A/D module is enabled. (For more information, see Section 20.3.4 “Special Event Trigger”.) 14.
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PIC18F66K80 FAMILY FIGURE 14-4: TIMER1 GATE COUNT ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 14.8.2 N TIMER1 GATE SOURCE SELECTION The Timer1 gate source can be selected from one of four sources. Source selection is controlled by the T1GSSx (T1GCON<1:0>) bits (see Table 14-4).
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PIC18F66K80 FAMILY 14.8.3 TIMER1 GATE TOGGLE MODE When Timer1 Gate Toggle mode is enabled, it is possible to measure the full cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. (For timing details, see Figure 14-5.) FIGURE 14-5: The T1GVAL bit (T1GCON<2>) indicates when the Toggled mode is active and the timer is counting.
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PIC18F66K80 FAMILY 14.8.4 TIMER1 GATE SINGLE PULSE MODE When Timer1 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Gate Single Pulse mode is enabled by setting the T1GSPM bit (T1GCON<4>) and the T1GGO/T1DONE bit (T1GCON<3>). The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T1GGO/ T1DONE bit will automatically be cleared.
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PIC18F66K80 FAMILY FIGURE 14-7: TIMER1 GATE SINGLE PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by Hardware on Falling Edge of T1GVAL Set by Software T1DONE Counting Enabled on Rising Edge of T1G T1G_IN T1CKI T1GVAL Timer1 TABLE 14-5: Name INTCON N+1 N N+2 N+4 N+3 REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX
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PIC18F66K80 FAMILY 15.
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PIC18F66K80 FAMILY 15.2 Timer2 Interrupt 15.3 Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the four-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag, which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>).
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PIC18F66K80 FAMILY 16.0 TIMER3 MODULE The Timer3 timer/counter modules incorporate these features: • Software selectable operation as a 16-bit timer or counter • Readable and writable eight-bit registers (TMR3H and TMR3L) • Selectable clock source (internal or external) with device clock or SOSC oscillator internal options • Interrupt-on-overflow • Module Reset on ECCP Special Event Trigger REGISTER 16-1: A simplified block diagram of the Timer3 module is shown in Figure 16-1.
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PIC18F66K80 FAMILY 16.1 Timer3 Gate Control Register The Timer3 Gate Control register (T3GCON), provided in Register 14-2, is used to control the Timer3 gate.
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PIC18F66K80 FAMILY REGISTER 16-3: OSCCON2: OSCILLATOR CONTROL REGISTER 2 U-0 R-0 U-0 RW-1 R/W-0 U-0 R-x R/W-0 — SOSCRUN — SOSCDRV(1) SOSCGO — MFIOFS MFIOSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 SOSCRUN: SOSC Run Status bit 1 = System clock comes from a secondary SOSC 0 = System clock comes from an oscillator other
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PIC18F66K80 FAMILY 16.2 The operating mode is determined by the clock select bits, TMR3CSx (T3CON<7:6>). When the TMR3CSx bits are cleared (= 00), Timer3 increments on every internal instruction cycle (FOSC/4). When TMR3CSx = 01, the Timer3 clock source is the system clock (FOSC), and when it is ‘10’, Timer3 works as a counter from the external clock from the T3CKI pin (on the rising edge after the first falling edge) or the SOSC oscillator.
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PIC18F66K80 FAMILY 16.3 Timer3 16-Bit Read/Write Mode Timer3 can be configured for 16-bit reads and writes (see Figure 16.3). When the RD16 control bit (T3CON<1>) is set, the address for TMR3H is mapped to a buffer register for the high byte of Timer3. A read from TMR3L will load the contents of the high byte of Timer3 into the Timer3 High Byte Buffer register.
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PIC18F66K80 FAMILY 16.5 TABLE 16-1: Timer3 Gates TIMER3 GATE ENABLE SELECTIONS Timer3 can be configured to count freely or the count can be enabled and disabled using the Timer3 gate circuitry. This is also referred to as the Timer3 gate count enable. T3CLK(†)  0 0 The Timer3 gate can also be driven by multiple selectable sources. Counts  0 1 Holds Count  1 0 Holds Count  1 1 Counts 16.5.
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PIC18F66K80 FAMILY 16.5.2 TIMER3 GATE SOURCE SELECTION The Timer3 gate source can be selected from one of four different sources. Source selection is controlled by the T3GSS<1:0> bits (T3GCON<1:0>). The polarity for each available source is also selectable and is controlled by the T3GPOL bit (T3GCON<6>).
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PIC18F66K80 FAMILY 16.5.4 TIMER3 GATE SINGLE PULSE MODE other gate events will be allowed to increment Timer3 until the T3GGO/T3DONE bit is once again set in software. When Timer3 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer3 Gate Single Pulse mode is first enabled by setting the T3GSPM bit (T3GCON<4>). Next, the T3GGO/ T3DONE bit (T3GCON<3>) must be set. Clearing the T3GSPM bit will also clear the T3GGO/ T3DONE bit. (For timing details, see Figure 16-4.
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PIC18F66K80 FAMILY FIGURE 16-5: TIMER3 GATE SINGLE PULSE AND TOGGLE COMBINED MODE TMR3GE T3GPOL T3GSPM T3GTM Cleared by Hardware on Falling Edge of T3GVAL Set by Software T3GGO/ T3DONE Counting Enabled on Rising Edge of T3G T3G_IN T3CKI T3GVAL Timer3 TMR3GIF 16.5.5 N N+1 Cleared by Software TIMER3 GATE VALUE STATUS When Timer3 gate value status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the T3GVAL bit (T3GCON<2>).
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PIC18F66K80 FAMILY 16.6 The module must be configured as either a timer or synchronous counter to take advantage of this feature. When used this way, the CCPR3H:CCPR3L register pair effectively becomes a Period register for Timer3. Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in the interrupt flag bit, TMR3IF. Table 16-3 gives each module’s flag bit.
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PIC18F66K80 FAMILY 17.0 TIMER4 MODULES The Timer4 timer modules have the following features: • • • • • • Eight-bit Timer register (TMR4) Eight-bit Period register (PR4) Readable and writable (all registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR4 match of PR4 The Timer4 modules have a control register shown in Register 17-1. Timer4 can be shut off by clearing control bit, TMR4ON (T4CON<2>), to minimize power consumption.
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PIC18F66K80 FAMILY 17.2 Timer4 Interrupt 17.3 The Timer4 module has an eight-bit Period register, PR4, that is both readable and writable. Timer4 increment from 00h until it matches PR4 and then resets to 00h on the next increment cycle. The PR4 register is initialized to FFh upon Reset. FIGURE 17-1: Output of TMR4 The outputs of TMR4 (before the postscaler) are used only as a PWM time base for the ECCP modules. They are not used as baud rate clocks for the MSSP module as is the Timer2 output.
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PIC18F66K80 FAMILY 18.
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PIC18F66K80 FAMILY 18.1 The CTMUCONH and CTMUCONL registers (Register 18-1 and Register 18-2) contain control bits for configuring the CTMU module edge source selection, edge source polarity selection, edge sequencing, A/D trigger, analog circuit capacitor discharge and enables. The CTMUICON register (Register 18-3) has bits for selecting the current source range and current source trim.
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PIC18F66K80 FAMILY REGISTER 18-2: CTMUCONL: CTMU CONTROL LOW REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 is programmed for a positive edge response 0 = Edge 2 is programmed for a negative edge response
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PIC18F66K80 FAMILY REGISTER 18-3: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change (+62% typ.) from nominal current 011110 . . .
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PIC18F66K80 FAMILY 18.2 CTMU Operation The CTMU works by using a fixed current source to charge a circuit. The type of circuit depends on the type of measurement being made. In the case of charge measurement, the current is fixed and the amount of time the current is applied to the circuit is fixed. The amount of voltage read by the A/D becomes a measurement of the circuit’s capacitance. In the case of time measurement, the current, as well as the capacitance of the circuit, is fixed.
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PIC18F66K80 FAMILY 18.2.5 INTERRUPTS The CTMU sets its interrupt flag (PIR3<3>) whenever the current source is enabled, then disabled. An interrupt is generated only if the corresponding interrupt enable bit (PIE3<3>) is also set. If edge sequencing is not enabled (i.e., Edge 1 must occur before Edge 2), it is necessary to monitor the edge status bits and determine which edge occurred last and caused the interrupt. 18.
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PIC18F66K80 FAMILY The CTMU current source may be trimmed with the trim bits in CTMUICON, using an iterative process to get the exact current desired. Alternatively, the nominal value without adjustment may be used. That value may be stored by software, for use in all subsequent capacitive or time measurements. To calculate the optimal value for RCAL, the nominal current must be chosen. For example, if the A/D Converter reference voltage is 3.3V, use 70% of full scale (or 2.
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PIC18F66K80 FAMILY EXAMPLE 18-1: SETUP FOR CTMU CALIBRATION ROUTINES #include "p18cxxx.
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PIC18F66K80 FAMILY EXAMPLE 18-2: CURRENT CALIBRATION ROUTINE #include "p18cxxx.h" #define COUNT 500 #define DELAY for(i=0;i
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PIC18F66K80 FAMILY 18.4.2 CAPACITANCE CALIBRATION There is a small amount of capacitance from the internal A/D Converter sample capacitor as well as stray capacitance from the circuit board traces and pads that affect the precision of capacitance measurements. A measurement of the stray capacitance can be taken by making sure the desired capacitance to be measured has been removed. After removing the capacitance to be measured: 1. 2. 3. 4. 5. 6. Initialize the A/D Converter and the CTMU.
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PIC18F66K80 FAMILY EXAMPLE 18-3: CAPACITANCE CALIBRATION ROUTINE #include "p18cxxx.h" #define #define #define #define #define #define COUNT 25 ETIME COUNT*2.5 DELAY for(i=0;i
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PIC18F66K80 FAMILY 18.5 Measuring Capacitance with the CTMU There are two ways to measure capacitance with the CTMU. The absolute method measures the actual capacitance value. The relative method only measures for any change in the capacitance. 18.5.1 ABSOLUTE CAPACITANCE MEASUREMENT For absolute capacitance measurements, both the current and capacitance calibration steps found in Section 18.4 “Calibrating the CTMU Module” should be followed. To perform these measurements: 1. 2. 3. 4. 5. 6. 7. 8.
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PIC18F66K80 FAMILY EXAMPLE 18-4: ROUTINE FOR CAPACITIVE TOUCH SWITCH #include "p18cxxx.h" #define #define #define #define COUNT 500 DELAY for(i=0;i
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PIC18F66K80 FAMILY 18.6 Measuring Time with the CTMU Module Time can be precisely measured after the ratio (C/I) is measured from the current and capacitance calibration step. To do that: 1. 2. 3. 4. 5. Initialize the A/D Converter and the CTMU. Set EDG1STAT. Set EDG2STAT. Perform an A/D conversion. Calculate the time between edges as T = (C/I) * V, where: • I is calculated in the current calibration step (Section 18.4.
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PIC18F66K80 FAMILY 18.7 Measuring Temperature with the CTMU The constant current source provided by the CTMU module can be used for low-cost temperature measurement by exploiting a basic property of common and inexpensive diodes. An on-chip temperature sense diode is provided on A/D Channel 29 to further simplify design and cost. 18.7.
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PIC18F66K80 FAMILY 18.8 An example use of the external capacitor feature is interfacing with variable capacitive-based sensors, such as a humidity sensor. As the humidity varies, the pulse-width output on CTPLS will vary. An example use of the CTDIN feature is interfacing with a digital sensor. The CTPLS output pin can be connected to an input capture pin and the varying pulse width measured to determine the sensor’s output in the application.
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PIC18F66K80 FAMILY 18.9 Measuring Temperature with the CTMU Module The CTMU, along with an internal diode, can be used to measure the temperature. The A/D can be connected to the internal diode and the CTMU module can EXAMPLE 18-6: source the current to the diode. The A/D reading will reflect the temperature. With the increase, the A/D readings will go low. This can be used for low-cost temperature measurement applications.
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PIC18F66K80 FAMILY case, if the module is performing an operation when Idle mode is invoked, the results will be similar to those with Sleep mode. 18.10 Operation During Sleep/Idle Modes 18.10.1 SLEEP MODE When the device enters any Sleep mode, the CTMU module current source is always disabled. If the CTMU is performing an operation that depends on the current source when Sleep mode is invoked, the operation may not terminate correctly. Capacitance and time measurements may return erroneous values. 18.
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PIC18F66K80 FAMILY 19.0 CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F66K80 family devices have four CCP (Capture/Compare/PWM) modules, designated CCP2 through CCP5. All the modules implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes. Note: Each CCP module contains a 16-bit register that can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register.
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PIC18F66K80 FAMILY REGISTER 19-2: CCPTMRS: CCP TIMER SELECT REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — C5TSEL C4TSEL C3TSEL C2TSEL C1TSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 C5TSEL: CCP5 Timer Selection bit 0 = CCP5 is based off of TMR1/TMR2 1 = CCP5 is based off of TMR3/TMR4 bit 3 C4TSEL: CCP4 Timer Selection bit
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PIC18F66K80 FAMILY REGISTER 19-3: CCPRxL: CCPx PERIOD LOW BYTE REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CCPRxL7 CCPRxL6 CCPRxL5 CCPRxL4 CCPRxL3 CCPRxL2 CCPRxL1 CCPRxL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown CCPRxL<7:0>: CCPx Period Register Low Byte bits Capture Mode: Capture register low byte Compare Mode: Compare register low byte
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PIC18F66K80 FAMILY 19.1 TABLE 19-1: CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 19.1.1 CCP MODULES AND TIMER RESOURCES The CCP modules utilize Timers, 1 through 4, varying with the selected mode.
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PIC18F66K80 FAMILY 19.2 19.2.1 Capture Mode In Capture mode, the appropriate CCPx pin should be configured as an input by setting the corresponding TRIS direction bit. In Capture mode, the CCPRxH:CCPRxL register pair captures the 16-bit value of the Timer register selected in the CCPTMRS when an event occurs on the CCPx pin. An event is defined as one of the following: • • • • 19.2.
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PIC18F66K80 FAMILY 19.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE bit (PIE4) clear to avoid false interrupts and should clear the flag bit, CCPxIF, following any such change in operating mode. 19.2.4 CCP PRESCALER There are four prescaler settings in Capture mode. They are specified as part of the operating mode selected by the mode select bits (CCPxM<3:0>).
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PIC18F66K80 FAMILY 19.3 Compare Mode 19.3.3 SOFTWARE INTERRUPT MODE In Compare mode, the 16-bit CCPRx register value is constantly compared against the Timer register pair value selected in the CCPTMR register. When a match occurs, the CCPx pin can be: When the Generate Software Interrupt mode is chosen (CCPxM<3:0> = 1010), the CCPx pin is not affected. Only a CCP interrupt is generated, if enabled, and the CCPxIE bit is set. • • • • 19.3.
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PIC18F66K80 FAMILY FIGURE 19-2: COMPARE MODE OPERATION BLOCK DIAGRAM CCPR5H Set CCP5IF CCPR5L Special Event Trigger (Timer1/3 Reset) CCP5 Pin Compare Match Comparator S Output Logic Q R TRIS Output Enable 4 CCP5CON<3:0> TMR1H TMR1L 0 TMR3H TMR3L 1 C5TSEL 0 TMR1H TMR1L 1 TMR3H TMR3L Special Event Trigger (Timer1/Timer3 Reset) C4TSEL Set CCP4IF Comparator CCPR4H CCPR4L Compare Match CCP4 Pin Output Logic 4 S Q R TRIS Output Enable CCP4CON<3:0> Note: This block diagram uses
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PIC18F66K80 FAMILY TABLE 19-3: Name INTCON REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1/3 Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF CM RI TO PD POR BOR IPEN SBOREN PIR3 — — RC2IF TX2IF CTMUIF CCP2IF CCP1IF — PIE3 — — RC2IE TX2IE CTMUIE CCP2IE CCP1IE — RCON IPR3 — — RC2IP TX2IP CTMUIP CCP2IP CCP1IP — PIR4 TMR4IF EEIF CMP2IF CMP1IF — CCP5IF CCP4IF CCP3IF PIE4 TMR4IE EEIE CMP2IE
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PIC18F66K80 FAMILY 19.4 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCPx pin is multiplexed with a PORTC or PORTB data latch, the appropriate TRIS bit must be cleared to make the CCPx pin an output. A PWM output (Figure 19-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
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PIC18F66K80 FAMILY 19.4.2 PWM DUTY CYCLE The PWM duty cycle is specified, to use CCP4 as an example, by writing to the CCPR4L register and to the CCP4CON<5:4> bits. Up to 10-bit resolution is available. The CCPR4L contains the eight MSbs and the CCP4CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR4L:CCP4CON<5:4>.
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PIC18F66K80 FAMILY TABLE 19-5: Name INTCON REGISTERS ASSOCIATED WITH PWM AND TIMERS Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF IPEN SBOREN CM RI TO PD POR BOR PIR3 — — RC2IF TX2IF CTMUIF CCP2IF CCP1IF — PIE3 — — RC2IE TX2IE CTMUIE CCP2IE CCP1IE — IPR3 — — RC2IP TX2IP CTMUIP CCP2IP CCP1IP — PIR4 TMR4IF EEIF CMP2IF CMP1IF — CCP5IF CCP4IF CCP3IF PIE4 TMR4IE EEIE CMP2IE CMP1IE — CCP5I
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PIC18F66K80 FAMILY 20.0 ENHANCED CAPTURE/COMPARE/PWM (ECCP) MODULE PIC18F66K80 family devices have one Enhanced Capture/Compare/PWM (ECCP) module: ECCP1. These modules contain a 16-bit register, which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. These ECCP modules are upward compatible with CCP ECCP1 is implemented as standard CCP modules with enhanced PWM capabilities. These include:  2010-2012 Microchip Technology Inc.
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PIC18F66K80 FAMILY REGISTER 20-1: CCP1CON: ENHANCED CAPTURE/COMPARE/PWM1 CONTROL R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 P1M<1:0>: Enhanced PWM Output Configuration bits If CCP1M<3:2> = 00, 01, 10: xx = P1A assigned as capture/compare input/output; P1B,
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PIC18F66K80 FAMILY REGISTER 20-2: CCPTMRS: CCP TIMER SELECT REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — C5TSEL C4TSEL C3TSEL C2TSEL C1TSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 C5TSEL: CCP5 Timer Selection bit 0 = CCP5 is based off of TMR1/TMR2 1 = CCP5 is based off of TMR3/TMR4 bit 3 C4TSEL: CCP4 Timer Selection bit
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PIC18F66K80 FAMILY In addition to the expanded range of modes available through the CCP1CON and ECCP1AS registers, the ECCP module has two additional registers associated with Enhanced PWM operation and auto-shutdown features. They are: • ECCP1DEL – Enhanced PWM Control • PSTR1CON – Pulse Steering Control 20.1 ECCP Outputs and Configuration The Enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode.
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PIC18F66K80 FAMILY 20.2.2 TIMER1/2/3/4 MODE SELECTION The timers that are to be used with the capture feature (Timer1 2, 3 or 4) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer to be used with each ECCP module is selected in the CCPTMRS register (Register 20-2). 20.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated.
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PIC18F66K80 FAMILY 20.3 20.3.2 Compare Mode TIMER1/2/3/4 MODE SELECTION In Compare mode, the 16-bit CCPR1 register value is constantly compared against the Timer register pair value selected in the CCPTMR1 register. When a match occurs, the ECCP1 pin can be: Timer1, 2, 3 or 4 must be running in Timer mode or Synchronized Counter mode if the ECCP module is using the compare feature. In Asynchronous Counter mode, the compare operation will not work reliably. • • • • 20.3.
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PIC18F66K80 FAMILY 20.4 The PWM outputs are multiplexed with I/O pins and are designated: P1A, P1B, P1C and P1D. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately. PWM (Enhanced Mode) The Enhanced PWM mode can generate a PWM signal on up to four different output pins with up to 10 bits of resolution. It can do this through four different PWM Output modes: • • • • Table 20-1 provides the pin assignments for each Enhanced PWM mode.
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PIC18F66K80 FAMILY TABLE 20-2: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode P1M<1:0> P1A P1B P1C P1D Single 00 Yes(1) Yes(1) Yes(1) Yes(1) Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: Outputs are enabled by pulse steering in Single mode (see Register 20-5).
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PIC18F66K80 FAMILY FIGURE 20-5: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) P1M<1:0> Signal PR2 + 1 Pulse Width 0 Period 00 (Single Output) P1A Modulated P1A Modulated 10 (Half-Bridge) Delay(1) Delay(1) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1L<7
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PIC18F66K80 FAMILY 20.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (see Figure 20-6). This mode can be used for half-bridge applications, as shown in Figure 20-7, or for full-bridge applications, where four power switches are being modulated with two PWM signals.
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PIC18F66K80 FAMILY 20.4.2 FULL-BRIDGE MODE In the Reverse mode, the P1C pin is driven to its active state and the P1B pin is modulated, while the P1A and P1D pins are driven to their inactive state, as provided Figure 20-9. In Full-Bridge mode, all four pins are used as outputs. An example of a full-bridge application is provided in Figure 20-8. The P1A, P1B, P1C and P1D outputs are multiplexed with the port data latches.
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PIC18F66K80 FAMILY FIGURE 20-9: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A (2) Pulse Width P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Pulse Width P1A(2) P1B(2) P1C(2) P1D(2) (1) Note 1: 2: (1) At this time, the TMR2 register is equal to the PR2 register. The output signal is shown as active-high. DS39977F-page 276  2010-2012 Microchip Technology Inc.
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PIC18F66K80 FAMILY 20.4.2.1 Direction Change in Full-Bridge Mode In the Full-Bridge mode, the P1M1 bit in the CCP1CON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the P1M1 bit of the CCP1CON register.
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PIC18F66K80 FAMILY FIGURE 20-11: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A P1B PW P1C P1D PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current Note 1: 20.4.3 All signals are shown as active-high. 2: TON is the turn-on delay of power switch, QC, and its driver. 3: TOFF is the turn-off delay of power switch, QD, and its driver.
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PIC18F66K80 FAMILY A shutdown condition is indicated by the ECCP1ASE (Auto-Shutdown Event Status) bit (ECCP1AS<7>). If the bit is a ‘0’, the PWM pins are operating normally. If the bit is a ‘1’, the PWM outputs are in the shutdown state. Each pin pair may be placed into one of three states: • Drive logic ‘1’ • Drive logic ‘0’ • Tri-state (high-impedance) When a shutdown event occurs, two things happen: • The ECCP1ASE bit is set to ‘1’.
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PIC18F66K80 FAMILY FIGURE 20-12: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (P1RSEN = 0) PWM Period Shutdown Event ECCP1ASE bit PWM Activity Normal PWM Start of PWM Period 20.4.5 Shutdown Event Occurs AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the P1RSEN bit (ECCP1DEL<7>).
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PIC18F66K80 FAMILY 20.4.6 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 20-14: In half-bridge applications, where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period until one switch completely turns off.
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PIC18F66K80 FAMILY REGISTER 20-4: ECCP1DEL: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 P1RSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCP1ASE bit clears automatically once the shutdown event goes away; the PWM restar
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PIC18F66K80 FAMILY REGISTER 20-5: PSTR1CON: PULSE STEERING CONTROL(1) R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 CMPL1 CMPL0 — STRSYNC STRD STRC STRB STRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 CMPL<1:0>: Complementary Mode Output Assignment Steering Sync bits 00 = See STR.
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PIC18F66K80 FAMILY FIGURE 20-16: 20.4.7.1 SIMPLIFIED STEERING BLOCK DIAGRAM(1,2) The STRSYNC bit of the PSTR1CON register gives the user two choices for when the steering event will happen. When the STRSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTR1CON register. In this case, the output signal at the P1 pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin.
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PIC18F66K80 FAMILY 20.4.8 OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2/4 will not increment and the state of the module will not change. If the ECCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. If Two-Speed Start-ups are enabled, the initial start-up frequency from HF-INTOSC and the postscaler may not be stable immediately.
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PIC18F66K80 FAMILY TABLE 20-3: File Name INTCON REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1/2/3/4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF IPEN SBOREN CM RI TO PD POR BOR PIR3 — — RC2IF TX2IF CTMUIF CCP2IF CCP1IF — PIE3 — — RC2IE TX2IE CTMUIE CCP2IE CCP1IE — RCON IPR3 — — RC2IP TX2IP CTMUIP CCP2IP CCP1IP — PIR4 TMR4IF EEIF CMP2IF CMP1IF — CCP5IF CCP4IF CCP3IF PIE4 TMR4IE EEIE
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PIC18F66K80 FAMILY 21.0 21.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE FIGURE 21-1: Internal Data Bus Read Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be devices such as serial EEPROMs, shift registers, display drivers and A/D Converters.
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PIC18F66K80 FAMILY 21.3.1 REGISTERS SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. The MSSP module has four registers for SPI mode operation. These are: In receive operations, SSPSR and SSPBUF together, create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set.
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PIC18F66K80 FAMILY REGISTER 21-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must b
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PIC18F66K80 FAMILY 21.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
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PIC18F66K80 FAMILY 21.3.4 ENABLING SPI I/O 21.3.5 To enable the serial port, MSSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins.
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PIC18F66K80 FAMILY 21.3.6 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 1, Figure 21-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
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PIC18F66K80 FAMILY 21.3.7 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data.
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PIC18F66K80 FAMILY FIGURE 21-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2 SSPSR to SSPBUF FIGURE 21-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 7 bit 6 bit 5 bit
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PIC18F66K80 FAMILY 21.3.9 OPERATION IN POWER-MANAGED MODES 21.3.10 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. In SPI Master mode, module clocks may be operating at a different speed than when in full-power mode; in the case of the Sleep mode, all clocks are halted. 21.3.11 BUS MODE COMPATIBILITY Table 21-1 shows the compatibility between the standard SPI modes, and the states of the CKP and CKE control bits.
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PIC18F66K80 FAMILY 21.4 I2C Mode 21.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support), and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing.
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PIC18F66K80 FAMILY REGISTER 21-3: R/W-0 SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE) R/W-0 SMP CKE R-0 R-0 R-0 D/A (1) (1) P S R-0 R/W (2,3) R-0 R-0 UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control is disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control is enabl
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PIC18F66K80 FAMILY REGISTER 21-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN(1) CKP SSPM3(2) SSPM2(2) SSPM1(2) SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C condi
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PIC18F66K80 FAMILY REGISTER 21-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MASTER MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit Unused in Master mode.
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PIC18F66K80 FAMILY REGISTER 21-6: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ SLAVE MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(1) RCEN(1) PEN(1) RSEN(1) SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit 1 = Enables interrupt when a general call address (0000h) is received in the SSPSR 0 = Ge
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PIC18F66K80 FAMILY 21.4.2 OPERATION The MSSP module functions are enabled by setting the MSSP Enable bit, SSPEN (SSPCON1<5>). The SSPCON1 register allows control of the I2C operation.
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PIC18F66K80 FAMILY 21.4.3.2 Address Masking Modes Masking an address bit causes that bit to become a “don’t care”. When one address bit is masked, two addresses will be Acknowledged and cause an interrupt. It is possible to mask more than one address bit at a time, which greatly expands the number of addresses Acknowledged. The I2C slave behaves the same way, whether address masking is used or not.
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PIC18F66K80 FAMILY 21.4.3.4 7-Bit Address Masking Mode Unlike 5-bit masking, 7-Bit Address Masking mode uses a mask of up to 8 bits (in 10-bit addressing) to define a range of addresses that can be Acknowledged, using the lowest bits of the incoming address. This allows the module to Acknowledge up to 127 different addresses with 7-bit addressing, or 255 with 10-bit addressing (see Example 21-3). This mode is the default configuration of the module, which is selected when MSSPMSK is unprogrammed (‘1’).
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PIC18F66K80 FAMILY 21.4.3.5 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit, BF (SSPSTAT<0>), is set or bit, SSPOV (SSPCON1<6>), is set.
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DS39977F-page 306 2 A6 Note 3 4 X 5 A3 Receiving Address A5 6 X 1 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPBUF is read 2 D6 6 D2 7 D1 8 D0 In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt. 9 D7 x = Don’t care (i.e., address bit can either be a ‘1’ or a ‘0’).
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DS39977F-page 308 2 1 3 1 Note 5 0 7 A8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 6 A9 8 9 2 X 4 5 A3 6 A2 4 5 6 Cleared in software 3 7 8 9 1 2 4 5 6 Cleared in software 3 D3 D2 Receive Data Byte D1 D0 ACK D7 D6 D5 D4 Cleared by hardware when SSPADD is updated with high byte of address 2 D3 D2 Note that the Most Significant bits of the address are not affected by the bit masking.
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DS39977F-page 310 2 1 3 1 CKP (SSPCON1<4>) UA (SSPSTAT<1>) BF (SSPSTAT<0>) 4 1 5 0 6 7 A9 A8 8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR SSPIF (PIR1<3> or PIR3<7>) 1 SCL S 1 9 ACK R/W = 0 1 3 4 5 Cleared in software 2 7 UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address 6 A6 A5 A4 A3 A2 A1 8 A0 Receive Second Byte of Address Dummy read of SSPBU
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PIC18F66K80 FAMILY 21.4.4 CLOCK STRETCHING Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. 21.4.4.
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PIC18F66K80 FAMILY 21.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCL output is forced to ‘0’. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has FIGURE 21-14: already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL.
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DS39977F-page 314 2 1 3 1 CKP (SSPCON<4>) UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) 4 1 5 0 6 7 A9 A8 8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR Cleared in software SSPIF (PIR1<3> or PIR3<7>) 1 SCL S 1 9 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 Cleared in software 3 A5 7 A1 8 A0 Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set.
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PIC18F66K80 FAMILY 21.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices.
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PIC18F66K80 FAMILY MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPMx bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware if the TRIS bits are set. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled.
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PIC18F66K80 FAMILY 21.4.6.1 I2C™ Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA while SCL outputs the serial clock.
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PIC18F66K80 FAMILY 21.4.7 BAUD RATE Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state. 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the 8 bits of the SSPADD register (Figure 21-19). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting.
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PIC18F66K80 FAMILY 21.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 21-20: SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting.
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PIC18F66K80 FAMILY 21.4.8 I2C™ MASTER MODE START CONDITION TIMING Note: To initiate a Start condition, the user sets the Start Enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low.
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PIC18F66K80 FAMILY 21.4.9 I2C™ MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting.
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PIC18F66K80 FAMILY 21.4.10 I2C™ MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address, is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification Parameter 106).
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DS39977F-page 324 S ACKEN SSPOV BF (SSPSTAT<0>) SDA = 0, SCL = 1, while CPU responds to SSPIF SSPIF SCL SDA 1 A7 2 4 5 6 Cleared in software 3 A6 A5 A4 A3 A2 Transmit Address to Slave 7 A1 8 9 R/W = 1 ACK ACK from Slave 2 3 5 6 7 8 D0 9 ACK 2 3 4 5 6 7 Cleared in software Set SSPIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 Cleared in software Set SSPIF at end of receive 9 ACK is not sent ACK Bus master terminates transfer
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PIC18F66K80 FAMILY 21.4.12 ACKNOWLEDGE SEQUENCE TIMING 21.4.13 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2<2>). At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to 0.
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PIC18F66K80 FAMILY 21.4.14 SLEEP OPERATION 21.4.17 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 21.4.15 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 21.4.
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PIC18F66K80 FAMILY 21.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL is sampled low at the beginning of the Start condition (Figure 21-28). SCL is sampled low before SDA is asserted low (Figure 21-29). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 21-30).
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PIC18F66K80 FAMILY FIGURE 21-29: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
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PIC18F66K80 FAMILY 21.4.17.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 21-31). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
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PIC18F66K80 FAMILY 21.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 21-33).
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PIC18F66K80 FAMILY TABLE 21-4: Name REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSPIF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSPIE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSPIP TMR1GIP TMR2IP TMR1IP INTCON PIR2 OSCFIF — — — BCLIF HLVDIF TMR3IF TMR3GIF PIE2 OSCFIE — — — BCLIE HLVDIE TMR3IE TMR3GIE
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PIC18F66K80 FAMILY 22.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of two serial I/O modules. (Generically, the EUSART is also known as a Serial Communications Interface or SCI.) The EUSART can be configured as a full-duplex, asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers.
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PIC18F66K80 FAMILY 22.1 EUSARTx Control Registers Note: The operation of each Enhanced USARTx module is controlled through three registers: • Transmit Status and Control (TXSTAx) • Receive Status and Control (RCSTAx) • Baud Rate Control (BAUDCONx) These are detailed on the following pages in Register 22-1, Register 22-2 and Register 22-3, respectively.
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PIC18F66K80 FAMILY REGISTER 22-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port is enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port is disabled (held in Re
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PIC18F66K80 FAMILY REGISTER 22-3: BAUDCONx: BAUD RATE CONTROL REGISTER R/W-0 R-1 R/W-x R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BR
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PIC18F66K80 FAMILY 22.2 Baud Rate Generator (BRG) The BRG is a dedicated, 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSARTx. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>) selects 16-bit mode. The SPBRGHx:SPBRGx register pair controls the period of a free-running timer. In Asynchronous mode, bits, BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>), also control the baud rate. In Synchronous mode, BRGH is ignored.
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PIC18F66K80 FAMILY EXAMPLE 22-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, and 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGHx:SPBRGx] + 1)) Solving for SPBRGHx:SPBRGx: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.
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PIC18F66K80 FAMILY TABLE 22-4: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 64.000 MHz Actual Rate (K) % Error SPBRG value (decimal) FOSC = 40.000 MHz Actual Rate (K) % Error SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate (K) % Error SPBRG value (decimal) FOSC = 10.000 MHz Actual Rate (K) % Error SPBRG value (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — — — — 1.221 1.73 255 1.202 0.16 129 2.4 — — — 2.441 1.
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PIC18F66K80 FAMILY TABLE 22-4: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 64.000 MHz Actual Rate (K) % Error SPBRG value (decimal) FOSC = 40.000 MHz Actual Rate (K) % Error FOSC = 20.000 MHz (decimal) Actual Rate (K) SPBRG value % Error FOSC = 10.000 MHz (decimal) Actual Rate (K) SPBRG value % Error SPBRG value (decimal) 0.3 0.300 0.00 13332 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 1.2 1.200 0.00 3332 1.200 0.
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PIC18F66K80 FAMILY 22.2.3 AUTO-BAUD RATE DETECT The Enhanced USARTx modules support the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source.
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PIC18F66K80 FAMILY FIGURE 22-1: BRG Value AUTOMATIC BAUD RATE CALCULATION XXXXh RXx pin 0000h 001Ch Start Edge #1 Bit 1 Bit 0 Edge #2 Bit 3 Bit 2 Edge #3 Bit 5 Bit 4 Edge #4 Bit 7 Bit 6 Edge #5 Stop Bit BRG Clock Auto-Cleared Set by User ABDEN bit RCxIF bit (Interrupt) Read RCREGx SPBRGx XXXXh 1Ch SPBRGHx XXXXh 00h Note: The ABD sequence requires the EUSARTx module to be configured in Asynchronous mode and WUE = 0.
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PIC18F66K80 FAMILY 22.3 Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx register is empty and the TXxIF flag bit is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXxIE. TXxIF will be set regardless of the state of TXxIE; it cannot be cleared in software. TXxIF is also not cleared immediately upon loading TXREGx, but becomes valid in the second instruction cycle following the load instruction.
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PIC18F66K80 FAMILY FIGURE 22-4: Write to TXREGx BRG Output (Shift Clock) ASYNCHRONOUS TRANSMISSION Word 1 TXx (pin) Start bit FIGURE 22-5: bit 1 bit 7/8 Stop bit Word 1 TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) bit 0 1 TCY Word 1 Transmit Shift Reg ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREGx Word 1 Word 2 BRG Output (Shift Clock) TXx (pin) TXxIF bit (Interrupt Reg. Flag) TRMT bit (Transmit Shift Reg.
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PIC18F66K80 FAMILY TABLE 22-6: Name REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSPIF TMR1GIF TMR2IF TMR1IF INTCON PIE1 PSPIE ADIE RC1IE TX1IE SSPIE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSPIP TMR1GIP TMR2IP TMR1IP PIR3 — — RC2IF TX2IF CTMUIF CCP2IF CCP1IF — PIE3 — — RC2IE TX2IE CTMUIE CCP2IE CCP1I
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PIC18F66K80 FAMILY 22.3.2 EUSARTx ASYNCHRONOUS RECEIVER 22.3.3 The receiver block diagram is shown in Figure 22-6. The data is received on the RXx pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems.
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PIC18F66K80 FAMILY FIGURE 22-7: ASYNCHRONOUS RECEPTION Start bit RXx (pin) bit 0 bit 7/8 Stop bit bit 1 Rcv Shift Reg Rcv Buffer Reg Start bit bit 0 Word 1 RCREGx Read Rcv Buffer Reg RCREGx bit 7/8 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREGx RCxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word causing the OERR (Overrun) bit to be set.
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PIC18F66K80 FAMILY 22.3.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the EUSARTx are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up due to activity on the RXx/DTx line while the EUSARTx is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCONx<1>).
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PIC18F66K80 FAMILY 22.3.4.2 Special Considerations Using the WUE Bit The timing of WUE and RCxIF events may cause some confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the EUSARTx in an Idle mode. The wake-up event causes a receive interrupt by setting the RCxIF bit. The WUE bit is cleared after this when a rising edge is seen on RXx/DTx. The interrupt condition is then cleared by reading the RCREGx register.
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PIC18F66K80 FAMILY 22.3.5 BREAK CHARACTER SEQUENCE The EUSARTx module has the capability of sending the special Break character sequences that are required by the LIN/J2602 bus standard. The Break character transmit consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTAx<3> and TXSTAx<5>, respectively) are set while the Transmit Shift Register is loaded with data.
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PIC18F66K80 FAMILY 22.4 Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx is empty and the TXxIF flag bit is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXxIE. TXxIF is set regardless of the state of enable bit, TXxIE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREGx register.
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PIC18F66K80 FAMILY FIGURE 22-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/CANRX/RX1/DT1/ CCP4 Pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/CANTX/TX1/CK1/ CCP3 Pin Write to TXREG1 reg TX1IF bit TRMT bit TXEN bit Note: This example is equally applicable to EUSART2 (RB6/PGC/TX2/CK2/KBI2 and RB7/PGD/T3G/RX2/DT2/KBI3).
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PIC18F66K80 FAMILY 22.4.2 EUSARTx SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTAx<5>) or the Continuous Receive Enable bit, CREN (RCSTAx<4>). Data is sampled on the RXx pin on the falling edge of the clock. If enable bit, SREN, is set, only a single word is received. If enable bit, CREN, is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence.
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PIC18F66K80 FAMILY TABLE 22-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSPIF TMR1GIF TMR2IF TMR1IF INTCON PIE1 PSPIE ADIE RC1IE TX1IE SSPIE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSPIP TMR1GIP TMR2IP TMR1IP PIR3 — — RC2IF TX2IF CTMUIF CCP2IF CCP1IF — PIE3 — — RC2IE TX2IE CTMUIE CCP2IE
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PIC18F66K80 FAMILY 22.5 e) EUSARTx Synchronous Slave Mode Synchronous Slave mode is entered by clearing bit, CSRC (TXSTAx<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CKx pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 22.5.1 To set up a Synchronous Slave Transmission: 1. 2. 3. 4. 5.
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PIC18F66K80 FAMILY 22.5.2 EUSARTx SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep, or any Idle mode and bit, SREN, which is a “don’t care” in Slave mode. 2. 3. 4. 5. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode.
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PIC18F66K80 FAMILY 23.0 12-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) Converter module in the PIC18F66K80 family of devices. It is a 13-bit differential A/D with 12-bit single-ended compatibility. It has inputs eight inputs for the 28-pin devices, 11 inputs for the 40/44-pin and 64-pin devices. This module allows conversion of an analog input signal to a corresponding 12-bit digital number.
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PIC18F66K80 FAMILY 23.2 A/D Registers 23.2.
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PIC18F66K80 FAMILY REGISTER 23-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x R/W-x R/W-x R/W-x TRIGSEL1 TRIGSEL0 VCFG1 VCFG0 VNCFG CHSN2 CHSN1 CHSN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 TRIGSEL<1:0>: Special Trigger Select bits 11 = Selects the special trigger from the CCP2 10 = Selects the special trigger from the Timer1 01 = Selects the special t
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PIC18F66K80 FAMILY REGISTER 23-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 TAD 110
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PIC18F66K80 FAMILY 23.2.2 A/D RESULT REGISTERS The ADRESH:ADRESL register pair is where the 12-bit A/D result and extended sign bits (ADSGNx) are loaded at the completion of a conversion. This register pair is 16 bits wide. The A/D module gives the flexibility of left or right justifying the 12-bit result in the 16-bit result register. The A/D Format Select bit (ADFM) controls this justification. Figure 23-3 shows the operation of the A/D result justification and the location of the sign bit (ADSGNx).
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PIC18F66K80 FAMILY REGISTER 23-4: ADRESH: A/D RESULT HIGH BYTE REGISTER, LEFT JUSTIFIED (ADFM = 0) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES11 ADRES10 ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 bit 7 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ADRES<11:4>: A/D Result High Byte bits REGISTER 23-5: ADRESL: A/D RESULT LOW BYTE REGISTER, LEFT JUSTIFIED (ADFM
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PIC18F66K80 FAMILY REGISTER 23-7: ADRESL: A/D RESULT LOW BYTE REGISTER, RIGHT JUSTIFIED (ADFM = 1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ADRES<7:0>: A/D Result Low Byte bits The ANCONx registers are used to configure the operation of the I/O pin associ
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PIC18F66K80 FAMILY REGISTER 23-9: ANCON1: A/D PORT CONFIGURATION REGISTER 1 U-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — ANSEL14(1) ANSEL13(1) ANSEL12(1) ANSEL11(1) ANSEL10 ANSEL9 ANSEL8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 ANSEL14: RD3/C2INB Pin Analog Enable bit(1) 1 = Pin is configured as an analog channel;
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PIC18F66K80 FAMILY FIGURE 23-4: A/D BLOCK DIAGRAM CHS<4:0> 11111 11110 11101 11100 11011 11010 12-Bit A/D Converter 1.
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PIC18F66K80 FAMILY After the A/D module has been configured as desired, the selected channel must be acquired before the conversion can start. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 23.3 “A/D Acquisition Requirements”. After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion. 2.
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PIC18F66K80 FAMILY 23.3 A/D Acquisition Requirements For the A/D Converter to meet its specified accuracy, the Charge Holding (CHOLD) capacitor must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 23-5. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD).
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PIC18F66K80 FAMILY 23.4 Selecting and Configuring Automatic Acquisition Time The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit.
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PIC18F66K80 FAMILY 23.7 ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). A/D Conversions Figure 23-6 shows the operation of the A/D Converter after the GO/DONE bit has been set and the ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins.
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PIC18F66K80 FAMILY 23.
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PIC18F66K80 FAMILY TABLE 23-2: Name REGISTERS ASSOCIATED WITH THE A/D MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSPIF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSPIE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSPIP TMR1GIP TMR2IP TMR1IP INTCON ADRESH A/D Result Register High Byte ADRESL A/D Result Register Low Byte ADCON0 — CHS4 CHS3 CHS2 CHS1
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PIC18F66K80 FAMILY NOTES: DS39977F-page 372  2010-2012 Microchip Technology Inc.
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PIC18F66K80 FAMILY 24.0 COMPARATOR MODULE 24.1 The analog comparator module contains two comparators that can be independently configured in a variety of ways. The inputs can be selected from the analog inputs and two internal voltage references. The digital outputs are available at the pin level and can also be read through the control register. Multiple output and interrupt event generation are also available. A generic single comparator from the module is shown in Figure 24-1.
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PIC18F66K80 FAMILY REGISTER 24-1: CMxCON: COMPARATOR CONTROL x REGISTER R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 6 COE: Comparator Output Enable bit 1 = Comparator output is pres
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PIC18F66K80 FAMILY REGISTER 24-2: CMSTAT: COMPARATOR STATUS REGISTER R-x R-x U-0 U-0 U-0 U-0 U-0 U-0 CMP2OUT CMP1OUT — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 CMP2OUT:CMP1OUT: Comparator x Status bits If CPOL (CMxCON<5>)= 0 (non-inverted polarity): 1 = Comparator x’s VIN+ > VIN0 = Comparator x’s VIN+ < VINIf CPOL = 1 (inverted polarity): 1 = Comparator x’s VI
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PIC18F66K80 FAMILY 24.2 Comparator Operation 24.3 Comparator Response Time A single comparator is shown in Figure 24-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input, VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input, VIN-, the output of the comparator is a digital high level.
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PIC18F66K80 FAMILY 24.5 Comparator Control and Configuration Each comparator has up to eight possible combinations of inputs: up to four external analog inputs and one of two internal voltage references. All of the comparators allow a selection of the signal from pin, CxINA, or the voltage from the comparator reference (CVREF) on the non-inverting channel. This is compared to either C1INB, CxINC, C2INB or the microcontroller’s fixed internal reference voltage (VBG, 1.
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PIC18F66K80 FAMILY FIGURE 24-4: COMPARATOR CONFIGURATIONS Comparator Off CON = 0, CREF = x, CCH<1:0> = xx COE VIN- Cx VIN+ Off (Read as ‘0’) Comparator CxINB > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 00 CxOUT Pin Comparator CxINC > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 01 COE CxINB CxINA COE VINVIN+ Cx CxOUT Pin Comparator C2INB/C1INB > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 10 CxINC VIN- CxINA VIN+ Cx Comparator VBG > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 11 COE C
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PIC18F66K80 FAMILY 24.6 Comparator Interrupts The comparator interrupt flag is set whenever any of the following occurs: • Low-to-high transition of the comparator output • High-to-low transition of the comparator output • Any change in the comparator output The comparator interrupt selection is done by the EVPOL<1:0> bits in the CMxCON register (CMxCON<4:3>). In order to provide maximum flexibility, the output of the comparator may be inverted using the CPOL bit in the CMxCON register (CMxCON<5>).
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PIC18F66K80 FAMILY 24.7 To minimize power consumption while in Sleep mode, turn off the comparators (CON = 0) before entering Sleep. If the device wakes up from Sleep, the contents of the CMxCON register are not affected. Comparator Operation During Sleep When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional, if enabled. This interrupt will wake-up the device from Sleep mode, when enabled.
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PIC18F66K80 FAMILY 25.0 COMPARATOR VOLTAGE REFERENCE MODULE EQUATION 25-1: If CVRSS = 1: ( The comparator voltage reference is a 32-tap resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. A block diagram of the module is shown in Figure 25-1.
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PIC18F66K80 FAMILY FIGURE 25-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ AVDD CVRSS = 1 CVRSS = 0 CVR<4:0> R CVREN R R 32-to-1 MUX R 32 Steps R CVREF R R VREF- CVRSS = 1 CVRSS = 0 25.2 Voltage Reference Accuracy/Error The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 25-1) keep CVREF from approaching the reference source rails.
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PIC18F66K80 FAMILY FIGURE 25-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18F66K80 CVREF Module R(1) Voltage Reference Output Impedance Note 1: TABLE 25-1: Name + – RA0 CVREF Output R is dependent upon the Voltage Reference Configuration bits, CVRCON<3:0> and CVRCON<5>.
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PIC18F66K80 FAMILY NOTES: DS39977F-page 384  2010-2012 Microchip Technology Inc.
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PIC18F66K80 FAMILY 26.0 HIGH/LOW-VOLTAGE DETECT (HLVD) The PIC18F66K80 family of devices has a High/LowVoltage Detect module (HLVD). This is a programmable circuit that sets both a device voltage trip point and the direction of change from that point. If the device experiences an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the program execution branches to the interrupt vector address and the software responds to the interrupt.
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PIC18F66K80 FAMILY The module is enabled by setting the HLVDEN bit (HLVDCON<4>). Each time the HLVD module is enabled, the circuitry requires some time to stabilize. The IRVST bit (HLVDCON<5>) is a read-only bit used to indicate when the circuit is stable. The module can only generate an interrupt after the circuit is stable and IRVST is set. trip point voltage.
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PIC18F66K80 FAMILY 26.2 HLVD Setup To set up the HLVD module: 1. 2. 3. 4. 5. Select the desired HLVD trip point by writing the value to the HLVDL<3:0> bits. Set the VDIRMAG bit to detect high voltage (VDIRMAG = 1) or low voltage (VDIRMAG = 0). Enable the HLVD module by setting the HLVDEN bit. Clear the HLVD interrupt flag (PIR2<2>), which may have been set from a previous interrupt.
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PIC18F66K80 FAMILY FIGURE 26-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0) HLVDIF may not be set CASE 1: VDD VHLVD HLVDIF Enable HLVD TIRVST IRVST Internal reference is stable CASE 2: HLVDIF cleared in software VDD VHLVD HLVDIF Enable HLVD TIRVST IRVST Internal reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists DS39977F-page 388  2010-2012 Microchip Technology Inc.
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PIC18F66K80 FAMILY FIGURE 26-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be set VHLVD VDD HLVDIF Enable HLVD TIRVST IRVST HLVDIF cleared in software Internal reference is stable CASE 2: VHLVD VDD HLVDIF Enable HLVD TIRVST IRVST Internal reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists Applications In many applications, it is desirable to detect a drop below, or rise above, a particular voltage
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PIC18F66K80 FAMILY 26.6 Operation During Sleep 26.7 When enabled, the HLVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 26-1: Effects of a Reset A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off.
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PIC18F66K80 FAMILY 27.0 ECAN MODULE PIC18F66K80 family devices contain an Enhanced Controller Area Network (ECAN) module. The ECAN module is fully backward compatible with the CAN module available in PIC18CXX8 and PIC18FXX8 devices and the ECAN module in PIC18Fxx80 devices. The Controller Area Network (CAN) module is a serial interface which is useful for communicating with other peripherals or microcontroller devices.
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PIC18F66K80 FAMILY BUFFERS 16 - 4 to 1 MUXs MESSAGE MSGREQ ABTF MLOA TXERR MTXBUFF MSGREQ ABTF MLOA TXERR MTXBUFF TXB2 MESSAGE TXB1 MESSAGE MSGREQ ABTF MLOA TXERR MTXBUFF TXB0 A c c e p t Acceptance Filters (RXF0-RXF05) MODE 0 Acceptance Filters (RXF06-RXF15) MODE 1, 2 MODE 0 2 RX Buffers Message Queue Control Transmit Byte Sequencer VCC Acceptance Mask RXM0 CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM Acceptance Mask RXM1 FIGURE 27-1: RXF15 Identifier Data Field M A B Rcv Byte MODE 1,
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PIC18F66K80 FAMILY 27.2 Note: CAN Module Registers Not all CAN registers are available in the Access Bank. There are many control and data registers associated with the CAN module. For convenience, their descriptions have been grouped into the following sections: • • • • • • • 27.2.1 CAN CONTROL AND STATUS REGISTERS The registers described in this section control the overall operation of the CAN module and show its operational status.
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PIC18F66K80 FAMILY REGISTER 27-1: CANCON: CAN CONTROL REGISTER Mode 0 R/W-1 REQOP2 R/W-0 REQOP1 R/W-0 REQOP0 R/S-0 ABAT R/W-0 WIN2 R/W-0 WIN1 R/W-0 WIN0 U-0 — Mode 1 R/W-1 REQOP2 R/W-0 REQOP1 R/W-0 REQOP0 R/S-0 ABAT U0 — U-0 — U-0 — U-0 — R/W-1 REQOP2 bit 7 R/W-0 REQOP1 R/W-0 REQOP0 R/S-0 ABAT R-0 FP3 R-0 FP2 R-0 FP1 R-0 FP0 Mode 2 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4 bit 3-1 bit 0 bit 4-0 Note 1: bit 0 S = Settable bit W = Writable bit ‘1’ = Bit is set
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PIC18F66K80 FAMILY REGISTER 27-2: Mode 0 Mode 1,2 CANSTAT: CAN STATUS REGISTER R-1 R-0 R-0 OPMODE2(1) OPMODE1(1) OPMODE0(1) bit 4 bit 3-1,4-0 W = Writable bit ‘1’ = Bit is set R-0 ICODE1 R-0 ICODE0 U-0 — R-0 EICODE2 R-0 EICODE1 R-0 EICODE0 bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown OPMODE<2:0>: Operation Mode Status bits(1) 111 = Reserved 110 = Reserved 101 = Reserved 100 = Configuration mode 011 = Listen Only mode 010 = Loopback mode 001 = Disable/Sleep mo
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PIC18F66K80 FAMILY EXAMPLE 27-1: CHANGING TO CONFIGURATION MODE ; Request Configuration mode. MOVLW B’10000000’ ; Set to Configuration Mode. MOVWF CANCON ; A request to switch to Configuration mode may not be immediately honored. ; Module will wait for CAN bus to be idle before switching to Configuration Mode. ; Request for other modes such as Loopback, Disable etc. may be honored immediately. ; It is always good practice to wait and verify before continuing.
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PIC18F66K80 FAMILY EXAMPLE 27-2: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS (CONTINUED) ErrorInterrupt BCF PIR3, ERRIF ; Clear the interrupt flag … ; Handle error.
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PIC18F66K80 FAMILY REGISTER 27-3: ECANCON: ENHANCED CAN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 MDSEL1(1) MDSEL0(1) FIFOWM(2) EWIN4 EWIN3 EWIN2 EWIN1 EWIN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 MDSEL<1:0>: Mode Select bits(1) 00 = Legacy mode (Mode 0, default) 01 = Enhanced Legacy mode (Mode 1) 10 = Enhanced FIFO mode (Mod
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PIC18F66K80 FAMILY REGISTER 27-4: Mode 0 Mode 1 Mode 2 COMSTAT: COMMUNICATION STATUS REGISTER R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0 RXB0OVFL RXB1OVFL TXBO TXBP RXBP TXWARN RXWARN EWARN R/C-0 R/C-0 R-0 R-0 R-0 R-0 R-0 R-0 — RXBnOVFL TXB0 TXBP RXBP TXWARN RXWARN EWARN R/C-0 R/C-0 FIFOEMPTY RXBnOVFL R-0 R-0 R-0 R-0 R-0 R-0 TXBO TXBP RXBP TXWARN RXWARN EWARN bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read
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PIC18F66K80 FAMILY 27.2.2 DEDICATED CAN TRANSMIT BUFFER REGISTERS This section describes the dedicated CAN Transmit Buffer registers and their associated control registers.
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PIC18F66K80 FAMILY REGISTER 27-6: TXBnSIDH: TRANSMIT BUFFER ‘n’ STANDARD IDENTIFIER REGISTERS, HIGH BYTE [0  n  2] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown SID<10:3>: Standard Identifier bits (if EXIDE (TXBnSIDL<3>) = 0) Extended Identifier bits, EID<28:21> (if
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PIC18F66K80 FAMILY REGISTER 27-9: TXBnEIDL: TRANSMIT BUFFER ‘n’ EXTENDED IDENTIFIER REGISTERS, LOW BYTE [0  n  2] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown EID<7:0>: Extended Identifier bits (not used when transmitting standard identifier message) REGISTER 27-10
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PIC18F66K80 FAMILY REGISTER 27-11: TXBnDLC: TRANSMIT BUFFER ‘n’ DATA LENGTH CODE REGISTERS [0  n  2] U-0 R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x — TXRTR — — DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 TXRTR: Transmit Remote Frame Transmission Request bit 1 = Transmitted message will have the TXRTR bit set 0 = Transmitted m
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PIC18F66K80 FAMILY EXAMPLE 27-3: TRANSMITTING A CAN MESSAGE USING BANKED METHOD ; Need to transmit Standard Identifier message 123h using TXB0 buffer. ; To successfully transmit, CAN module must be either in Normal or Loopback mode. ; TXB0 buffer is not in access bank. And since we want banked method, we need to make sure ; that correct bank is selected. BANKSEL TXB0CON ; One BANKSEL in beginning will make sure that we are ; in correct bank for rest of the buffer access.
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PIC18F66K80 FAMILY EXAMPLE 27-4: TRANSMITTING A CAN MESSAGE USING WIN BITS ; Need to transmit Standard Identifier message 123h using TXB0 buffer. ; To successfully transmit, CAN module must be either in Normal or Loopback mode. ; TXB0 buffer is not in access bank. Use WIN bits to map it to RXB0 area. MOVF CANCON, W ; WIN bits are in lower 4 bits only. Read CANCON ; register to preserve all other bits. If operation ; mode is already known, there is no need to preserve ; other bits.
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PIC18F66K80 FAMILY 27.2.3 DEDICATED CAN RECEIVE BUFFER REGISTERS This section shows the dedicated CAN Receive Buffer registers with their associated control registers.
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PIC18F66K80 FAMILY REGISTER 27-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER (CONTINUED) bit 2 Mode 0: RB0DBEN: Receive Buffer 0 Double-Buffer Enable bit 1 = Receive Buffer 0 overflow will write to Receive Buffer 1 0 = No Receive Buffer 0 overflow to Receive Buffer 1 Mode 1, 2: FILHIT<4:0>: Filter Hit bit 2 This bit combines with other bits to form filter acceptance bits<4:0>.
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PIC18F66K80 FAMILY REGISTER 27-14: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER Mode 0 Mode 1,2 R/C-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R-0 R-0 RXFUL(1) RXM1 RXM0 — RXRTRRO FILHIT2 FILHIT1 FILHIT0 R/C-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 RXM1 RTRRO FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 (1) RXFUL bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 bit 6-5, 6 x
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PIC18F66K80 FAMILY REGISTER 27-14: RXB1CON: RECEIVE BUFFER 1 CONTROL REGISTER (CONTINUED) bit 2-0 Note 1: Mode 0: FILHIT<2:0>: Filter Hit bits These bits indicate which acceptance filter enabled the last message reception into Receive Buffer 1.
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PIC18F66K80 FAMILY REGISTER 27-16: RXBnSIDL: RECEIVE BUFFER ‘n’ STANDARD IDENTIFIER REGISTERS, LOW BYTE [0  n  1] R-x R-x R-x R-x R-x U-0 R-x R-x SID2 SID1 SID0 SRR EXID — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 SID<2:0>: Standard Identifier bits (if EXID = 0) Extended Identifier bits, EID<20:18> (if EXID = 1).
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PIC18F66K80 FAMILY REGISTER 27-19: RXBnDLC: RECEIVE BUFFER ‘n’ DATA LENGTH CODE REGISTERS [0  n  1] U-0 R-x R-x R-x R-x R-x R-x R-x — RXRTR RB1 R0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 RXRTR: Receiver Remote Transmission Request bit 1 = Remote transfer request 0 = No remote transfer request bit 5 RB1: Reserved bi
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PIC18F66K80 FAMILY REGISTER 27-21: RXERRCNT: RECEIVE ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown REC<7:0>: Receive Error Counter bits This register contains the receive error value as defined by the CAN specifications.
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PIC18F66K80 FAMILY 27.2.3.1 Programmable TX/RX and Auto-RTR Buffers The ECAN module contains 6 message buffers that can be programmed as transmit or receive buffers. Any of these buffers can also be programmed to automatically handle RTR messages. These registers are not used in Mode 0.
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PIC18F66K80 FAMILY REGISTER 27-23: BnCON: TX/RX BUFFER ‘n’ CONTROL REGISTERS IN TRANSMIT MODE [0  n  5, TXnEN (BSEL0) = 1](1) R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TXBIF(3) TXABT(3) TXLARB(3) TXERR(3) TXREQ(2,4) RTREN TXPRI1(5) TXPRI0(5) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TXBIF: Transmit Buffer Interrupt Flag bit(3) 1 = A message was succe
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PIC18F66K80 FAMILY REGISTER 27-24: BnSIDH: TX/RX BUFFER ‘n’ STANDARD IDENTIFIER REGISTERS, HIGH BYTE IN RECEIVE MODE [0  n  5, TXnEN (BSEL0) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown SID<10:3>: Standard Identifier bits (if EXIDE (BnSIDL<3>) = 0) Extended Ident
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PIC18F66K80 FAMILY REGISTER 27-26: BnSIDL: TX/RX BUFFER ‘n’ STANDARD IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0  n  5, TXnEN (BSEL0) = 0](1) R-x R-x R-x R-x R-x U-0 R-x R-x SID2 SID1 SID0 SRR EXIDE — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 SID<2:0>: Standard Identifier bits (if EXID = 0) Extended Identifier bits, EID<20:18> (if
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PIC18F66K80 FAMILY REGISTER 27-28: BnEIDH: TX/RX BUFFER ‘n’ EXTENDED IDENTIFIER REGISTERS, HIGH BYTE IN RECEIVE MODE [0  n  5, TXnEN (BSEL0) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown EID<15:8>: Extended Identifier bits These registers are available in Mod
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PIC18F66K80 FAMILY REGISTER 27-31: BnEIDL: TX/RX BUFFER ‘n’ EXTENDED IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0  n  5, TXnEN (BSEL) = 1](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 FEID4 EID3 EID2 EID1 EID0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared EID<7:0>: Extended Identifier bits bit 7-0 Note 1: x = Bit is unknown These registers are availabl
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PIC18F66K80 FAMILY REGISTER 27-34: BnDLC: TX/RX BUFFER ‘n’ DATA LENGTH CODE REGISTERS IN RECEIVE MODE [0  n  5, TXnEN (BSEL) = 0](1) U-0 R-x R-x R-x R-x R-x R-x R-x — RXRTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 RXRTR: Receiver Remote Transmission Request bit 1 = This is a remote transmission request 0 =
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PIC18F66K80 FAMILY REGISTER 27-35: BnDLC: TX/RX BUFFER ‘n’ DATA LENGTH CODE REGISTERS IN TRANSMIT MODE [0  n  5, TXnEN (BSEL) = 1](1) U-0 R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x — TXRTR — — DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 TXRTR: Transmitter Remote Transmission Request bit 1 = Transmitted message will have th
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PIC18F66K80 FAMILY 27.2.3.2 Message Acceptance Filters and Masks This section describes the message acceptance filters and masks for the CAN receive buffers.
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PIC18F66K80 FAMILY REGISTER 27-39: RXFnEIDH: RECEIVE ACCEPTANCE FILTER ‘n’ EXTENDED IDENTIFIER REGISTERS, HIGH BYTE [0  n  15](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown EID<15:8>: Extended Identifier Filter bits Registers, RXF6EIDH:RXF15EIDH, are
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PIC18F66K80 FAMILY REGISTER 27-42: RXMnSIDL: RECEIVE ACCEPTANCE MASK ‘n’ STANDARD IDENTIFIER MASK REGISTERS, LOW BYTE [0  n  1] R/W-x R/W-x R/W-x U-0 R/W-0 U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDEN(1) — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 SID<2:0>: Standard Identifier Mask bits or Extended Identifier Mask bits (EID<20:18>) bit 4 Unim
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PIC18F66K80 FAMILY REGISTER 27-45: RXFCONn: RECEIVE FILTER CONTROL REGISTER ‘n’ [0  n  1](1) RXFCON0 RXFCON1 R/W-0 RXF7EN R/W-0 RXF6EN R/W-0 RXF5EN R/W-0 RXF4EN R/W-0 RXF3EN R/W-0 RXF2EN R/W-0 RXF1EN R/W-0 RXF0EN R/W-0 RXF15EN bit 7 R/W-0 RXF14EN R/W-0 RXF13EN R/W-0 R/W-0 RXF12EN RXF11EN R/W-0 RXF10EN R/W-0 RXF9EN R/W-0 RXF8EN bit 0 Legend: R = Readable bit -n = Value at POR bit 7-0 Note 1: Note: W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared
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PIC18F66K80 FAMILY REGISTER 27-47: RXFBCONn: RECEIVE FILTER BUFFER CONTROL REGISTER ‘n’(1) RXFBCON0 R/W-0 F1BP_3 R/W-0 F1BP_2 R/W-0 F1BP_1 R/W-0 F1BP_0 R/W-0 F0BP_3 R/W-0 F0BP_2 R/W-0 F0BP_1 R/W-0 F0BP_0 RXFBCON1 R/W-0 F3BP_3 R/W-0 F3BP_2 R/W-0 F3BP_1 R/W-1 F3BP_0 R/W-0 F2BP_3 R/W-0 F2BP_2 R/W-0 F2BP_1 R/W-1 F2BP_0 RXFBCON2 R/W-0 F5BP_3 R/W-0 F5BP_2 R/W-0 F5BP_1 R/W-1 F5BP_0 R/W-0 F4BP_3 R/W-0 F4BP_2 R/W-0 F4BP_1 R/W-1 F4BP_0 RXFBCON3 R/W-0 F7BP_3 R/W-0 F7BP_2 R/W-0 F7BP_1 R/W
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PIC18F66K80 FAMILY REGISTER 27-48: MSEL0: MASK SELECT REGISTER 0(1) R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 FIL3_1 FIL3_0 FIL2_1 FIL2_0 FIL1_1 FIL1_0 FIL0_1 FIL0_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 FIL3_<1:0>: Filter 3 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL2_<1:0>: Filter 2 Select bits 1 a
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PIC18F66K80 FAMILY REGISTER 27-49: MSEL1: MASK SELECT REGISTER 1(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 FIL7_1 FIL7_0 FIL6_1 FIL6_0 FIL5_1 FIL5_0 FIL4_1 FIL4_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 FIL7_<1:0>: Filter 7 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL6_<1:0>: Filter 6 Select bits 1 a
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PIC18F66K80 FAMILY REGISTER 27-50: MSEL2: MASK SELECT REGISTER 2(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FIL11_1 FIL11_0 FIL10_1 FIL10_0 FIL9_1 FIL9_0 FIL8_1 FIL8_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 FIL11_<1:0>: Filter 11 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL10_<1:0>: Filter 10 Select
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PIC18F66K80 FAMILY REGISTER 27-51: MSEL3: MASK SELECT REGISTER 3(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FIL15_1 FIL15_0 FIL14_1 FIL14_0 FIL13_1 FIL13_0 FIL12_1 FIL12_0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 FIL15_<1:0>: Filter 15 Select bits 1 and 0 11 = No mask 10 = Filter 15 01 = Acceptance Mask 1 00 = Acceptance Mask 0 bit 5-4 FIL14_<1:0>: Filter 14 Sel
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PIC18F66K80 FAMILY 27.2.4 CAN BAUD RATE REGISTERS This section describes the CAN Baud Rate registers. Note: These registers are Configuration mode only.
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PIC18F66K80 FAMILY REGISTER 27-53: BRGCON2: BAUD RATE CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SEG2PHTS: Phase Segment 2 Time Select bit 1 = Freely programmable 0 = Maximum of PHEG1 or Information Processing Time (IPT), whichever i
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PIC18F66K80 FAMILY REGISTER 27-54: BRGCON3: BAUD RATE CONTROL REGISTER 3 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 WAKDIS WAKFIL — — — SEG2PH2(1) R/W-0 R/W-0 SEG2PH1(1) SEG2PH0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WAKDIS: Wake-up Disable bit 1 = Disable CAN bus activity wake-up feature 0 = Enable CAN bus activity wake-up feature bit 6 WAKFIL: Selects CAN bus Line Filter for Wak
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PIC18F66K80 FAMILY 27.2.5 CAN MODULE I/O CONTROL REGISTER This register controls the operation of the CAN module’s I/O pins in relation to the rest of the microcontroller.
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PIC18F66K80 FAMILY 27.2.6 CAN INTERRUPT REGISTERS The registers in this section are the same as described in Section 10.0 “Interrupts”. They are duplicated here for convenience.
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PIC18F66K80 FAMILY REGISTER 27-57: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5 Mode 0 Mode 1 R/W-0 IRXIE R/W-0 WAKIE R/W-0 ERRIE R/W-0 TXB2IE R/W-0 TXB1IE(1) R/W-0 TXB0IE(1) R/W-0 RXB1IE R/W-0 RXB0IE R/W-0 IRXIE bit 7 R/W-0 WAKIE R/W-0 ERRIE R/W-0 TXBnIE R/W-0 TXB1IE(1) R/W-0 TXB0IE(1) R/W-0 RXBnIE R/W-0 FIFOWMIE bit 0 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read
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PIC18F66K80 FAMILY REGISTER 27-58: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5 Mode 0 Mode 1,2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IRXIP WAKIP ERRIP TXB2IP TXB1IP(1) TXB0IP(1) RXB1IP RXB0IP R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RXBnIP FIFOWMIP IRXIP WAKIP ERRIP (1) TXBnIP TXB1IP (1) TXB0IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7
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PIC18F66K80 FAMILY REGISTER 27-59: TXBIE: TRANSMIT BUFFERS INTERRUPT ENABLE REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — — TXB2IE(2) TXB1IE(2) TXB0IE(2) — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-2 TXB2IE:TXB0IE: Transmit Buffer 2-0 Interrupt Enable bits(2) 1 = Transmit buffer interrupt is enabled 0 = Transmit buffer interrupt
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PIC18F66K80 FAMILY 27.3 CAN Modes of Operation The PIC18F66K80 family has six main modes of operation: • • • • • • Configuration mode Disable/Sleep mode Normal Operation mode Listen Only mode Loopback mode Error Recognition mode All modes, except Error Recognition, are requested by setting the REQOP bits (CANCON<7:5>). Error Recognition mode is requested through the RXM bits of the Receive Buffer register(s). Entry into a mode is Acknowledged by monitoring the OPMODE bits.
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PIC18F66K80 FAMILY 27.3.4 LISTEN ONLY MODE Listen Only mode provides a means for the PIC18F66K80 family devices to receive all messages, including messages with errors. This mode can be used for bus monitor applications or for detecting the baud rate in ‘hot plugging’ situations. For auto-baud detection, it is necessary that there are at least two other nodes which are communicating with each other. The baud rate can be detected empirically by testing different values until valid messages are received.
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PIC18F66K80 FAMILY 27.4.3 MODE 2 – ENHANCED FIFO MODE In Mode 2, two or more receive buffers are used to form the receive FIFO (first in, first out) buffer. There is no one-to-one relationship between the receive buffer and acceptance filter registers. Any filter that is enabled and linked to any FIFO receive buffer can generate acceptance and cause FIFO to be updated. FIFO length is user-programmable, from 2-8 buffers deep.
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PIC18F66K80 FAMILY 27.5.4 PROGRAMMABLE AUTO-RTR BUFFERS In Mode 1 and 2, any of six programmable transmit/ receive buffers may be programmed to automatically respond to predefined RTR messages without user firmware intervention. Automatic RTR handling is enabled by setting the TX2EN bit in the BSEL0 register and the RTREN bit in the BnCON register.
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PIC18F66K80 FAMILY TRANSMIT PRIORITY transmit buffer with the highest priority will be sent first. If two buffers have the same priority setting, the buffer with the highest buffer number will be sent first. There are four levels of transmit priority. If the TXP bits for a particular message buffer are set to ‘11’, that buffer has the highest possible priority. If the TXP bits for a particular message buffer are set to ‘00’, that buffer has the lowest possible priority.
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PIC18F66K80 FAMILY 27.7 27.7.1 Message Reception RECEIVING A MESSAGE Of all receive buffers, the MAB is always committed to receiving the next message from the bus. The MCU can access one buffer while the other buffer is available for message reception or holding a previously received message. Note: The entire contents of the MAB are moved into the receive buffer once a message is accepted.
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PIC18F66K80 FAMILY 27.7.3 ENHANCED FIFO MODE When configured for Mode 2, two of the dedicated receive buffers in combination with one or more programmable transmit/receive buffers, are used to create a maximum of an 8 buffers deep FIFO buffer. In this mode, there is no direct correlation between filters and receive buffer registers. Any filter that has been enabled can generate an acceptance.
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PIC18F66K80 FAMILY In Mode 1 and 2, there are an additional 10 acceptance filters, RXF6-RXF15, creating a total of 16 available filters. RXF15 can be used either as an acceptance filter or acceptance mask register. Each of these acceptance filters can be individually enabled or disabled by setting or clearing the RXFENn bit in the RXFCONn register. Any of these 16 acceptance filters can be dynamically associated with any of the receive buffers.
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PIC18F66K80 FAMILY 27.9 Baud Rate Setting All nodes on a given CAN bus must have the same nominal bit rate. The CAN protocol uses Non-Returnto-Zero (NRZ) coding which does not encode a clock within the data stream. Therefore, the receive clock must be recovered by the receiving nodes and synchronized to the transmitter’s clock.
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PIC18F66K80 FAMILY 27.9.1 EXTERNAL CLOCK, INTERNAL CLOCK AND MEASURABLE JITTER IN HS-PLL BASED OSCILLATORS The microcontroller clock frequency generated from a PLL circuit is subject to a jitter, also defined as Phase Jitter or Phase Skew. For its PIC18 Enhanced microcontrollers, Microchip specifies phase jitter (Pjitter) as being 2% (Gaussian distribution, within 3 standard deviations, see Parameter F13 in Table 31-7) and Total Jitter (Tjitter) as being 2 * Pjitter.
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PIC18F66K80 FAMILY Table 27-2 shows the relation between the clock generated by the PLL and the frequency error from jitter (measured jitter-induced error of 2%, Gaussian distribution, within 3 standard deviations), as a percentage of the nominal clock frequency. TABLE 27-2: This is clearly smaller than the expected drift of a crystal oscillator, typically specified at 100 ppm or 0.01%. If we add jitter to oscillator drift, we have a total frequency drift of 0.0132%.
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PIC18F66K80 FAMILY 27.9.2 TIME QUANTA 27.9.3 SYNCHRONIZATION SEGMENT As already mentioned, the Time Quanta is a fixed unit derived from the oscillator period and baud rate prescaler. Its relationship to TBIT and the Nominal Bit Rate is shown in Example 27-6. This part of the bit time is used to synchronize the various CAN nodes on the bus. The edge of the input signal is expected to occur during the sync segment. The duration is 1 TQ. EXAMPLE 27-6: 27.9.
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PIC18F66K80 FAMILY 27.10 Synchronization To compensate for phase shifts between the oscillator frequencies of each of the nodes on the bus, each CAN controller must be able to synchronize to the relevant signal edge of the incoming signal. When an edge in the transmitted data is detected, the logic will compare the location of the edge to the expected time (Sync_Seg). The circuit will then adjust the values of Phase Segment 1 and Phase Segment 2 as necessary.
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PIC18F66K80 FAMILY FIGURE 27-7: Sync SHORTENING A BIT PERIOD (SUBTRACTING SJW FROM PHASE SEGMENT 2) Prop Segment Phase Segment 1 TQ Phase Segment 2  SJW Sample Point Actual Bit Length Nominal Bit Length 27.11 Programming Time Segments Some requirements for programming of the time segments: • Prop_Seg + Phase_Seg 1  Phase_Seg 2 • Phase_Seg 2  Sync Jump Width. For example, assume that a 125 kHz CAN baud rate is desired, using 20 MHz for FOSC.
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PIC18F66K80 FAMILY 27.13 Bit Timing Configuration Registers The Baud Rate Control registers (BRGCON1, BRGCON2, BRGCON3) control the bit timing for the CAN bus interface. These registers can only be modified when the PIC18F66K80 family devices are in Configuration mode. 27.13.1 BRGCON1 The BRP bits control the baud rate prescaler. The SJW<1:0> bits select the synchronization jump width in terms of multiples of TQ. 27.13.2 BRGCON2 27.14.
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PIC18F66K80 FAMILY The PIC18F66K80 family devices are error-active if both error counters are below the error-passive limit of 128. They are error-passive if at least one of the error counters equals or exceeds 128. They go to bus-off if the transmit error counter equals or exceeds the busoff limit of 256. The devices remain in this state until the bus-off recovery sequence is finished. The bus-off recovery sequence consists of 128 occurrences of 11 consecutive recessive bits (see Figure 27-8).
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PIC18F66K80 FAMILY 27.15.1 INTERRUPT CODE BITS To simplify the interrupt handling process in user firmware, the ECAN module encodes a special set of bits. In Mode 0, these bits are ICODE<3:1> in the CANSTAT register. In Mode 1 and 2, these bits are EICODE<4:0> in the CANSTAT register. Interrupts are internally prioritized such that the higher priority interrupts are assigned lower values.
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PIC18F66K80 FAMILY 27.15.6.1 Receiver Overflow An overflow condition occurs when the MAB has assembled a valid received message (the message meets the criteria of the acceptance filters) and the receive buffer associated with the filter is not available for loading of a new message. The associated RXBnOVFL bit in the COMSTAT register will be set to indicate the overflow condition. This bit must be cleared by the MCU. 27.15.6.
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PIC18F66K80 FAMILY NOTES: DS39977F-page 456  2010-2012 Microchip Technology Inc.
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PIC18F66K80 FAMILY 28.0 SPECIAL FEATURES OF THE CPU The PIC18F66K80 family of devices includes several features intended to maximize reliability and minimize cost through elimination of external components.
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PIC18F66K80 FAMILY TABLE 28-1: CONFIGURATION BITS AND DEVICE IDs File Name Bit 7 Bit 6 Bit 5 300000h CONFIG1L — XINST — 300001h CONFIG1H IESO FCMEN — 300002h CONFIG2L — 300003h CONFIG2H — BORPWR1 BORWPR0 WDTPS4 WDTPS3 Bit 4 Bit 3 Bit 2 SOSCSEL1 SOSCSEL0 INTOSCSEL Default/ Unprogrammed Value Bit 1 Bit 0 — RETEN -1-1 11-1 PLLCFG FOSC3 FOSC2 FOSC1 FOSC0 00-0 1000 BORV1 BORV0 BOREN1 BOREN0 PWRTEN -111 1111 WDTPS2 WDTPS1 WDTPS0 WDTEN1 WDTEN0 -111 1111 (1,3) MSSPMSK
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PIC18F66K80 FAMILY REGISTER 28-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h) U-0 R/P-1 U-0 — XINST — R/P-1 R/P-1 SOSCSEL1 SOSCSEL0 R/P-1 U-0 R/P-1 INTOSCSEL — RETEN bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension
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PIC18F66K80 FAMILY REGISTER 28-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 R/P-0 U-0 U-0 R/P-1 R/P-0 R/P-0 R/P-0 IESO FCMEN — PLLCFG(1) FOSC3(2) FOSC2(2) FOSC1(2) FOSC0(2) bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Two-Speed Start-up is enabled 0 = Two
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PIC18F66K80 FAMILY REGISTER 28-3: U-0 — CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) R/P-1 BORPWR1 R/P-1 (1) R/P-1 (1) BORPWR0 BORV1 R/P-1 (1) BORV0 (1) R/P-1 R/P-1 (2) BOREN1 R/P-1 (2) BOREN0 PWRTEN(2) bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-5 BORPWR<1:0>: BORMV Power-Level bits
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PIC18F66K80 FAMILY REGISTER 28-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN1 WDTEN0 bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-2 WDTPS<4:0>: Watchdog Timer Postscale Select bits 11111 = Res
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PIC18F66K80 FAMILY REGISTER 28-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 MCLRE — — — MSSPMSK T3CKMX(1) T0CKMX(1) CANMX bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin is enabled; RE3 input pin is disabled 0 = RE3 input pin is enabled
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PIC18F66K80 FAMILY REGISTER 28-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 U-0 U-0 R/P-0 U-0 U-0 U-0 R/P-1 DEBUG — — BBSIZ0 — — — STVREN bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled, RB6 and RB7 are configured as general purpose I/O pi
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PIC18F66K80 FAMILY REGISTER 28-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — CP3 CP2 CP1 CP0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 CP3: Code Protection bit 1 = Block 3 is not code-protected(1) 0 = Block 3 is code-protected(1) bit 2 CP2: Code Prot
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PIC18F66K80 FAMILY REGISTER 28-8: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB — — — — — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM is not code-protected 0 = Data EEPROM is code-protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot
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PIC18F66K80 FAMILY REGISTER 28-9: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — WRT3 WRT2 WRT1 WRT0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRT3: Write Protection bit 1 = Block 3 is not write-protected(1) 0 = Block 3 is write-protected(1) bit 2 WRT2:
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PIC18F66K80 FAMILY REGISTER 28-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) R/C-1 R/C-1 R-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC(1) — — — — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM is not write-protected 0 = Data EEPROM is write-protected bit 6 WRTB: Boot Block Write Protection
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PIC18F66K80 FAMILY REGISTER 28-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — EBTR3 EBTR2 EBTR1 EBTR0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 EBTR3: Table Read Protection bit 1 = Block 3 is not protected from table reads executed in other blocks(1) 0 =
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PIC18F66K80 FAMILY REGISTER 28-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh) U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB — — — — — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit 1 = Boot block is not protected from table reads executed in othe
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PIC18F66K80 FAMILY REGISTER 28-13: DEVID1: DEVICE ID REGISTER 1 FOR THE PIC18F66K80 FAMILY R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 DEV<2:0>: Device ID bits These bits are used with the DEV<10:3> bits in the Device ID Register 2 to identify the part number: 000 = PIC18F46K80, PIC18LF26K80 001 = PI
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PIC18F66K80 FAMILY 28.2 The WDT can be operated in one of four modes as determined by WDTEN<1:0> (CONFIG2H<1:0>. The four modes are: Watchdog Timer (WDT) For the PIC18F66K80 family of devices, the WDT is driven by the LF-INTOSC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the LF-INTOSC oscillator.
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PIC18F66K80 FAMILY 28.2.1 CONTROL REGISTER Register 28-15 shows the WDTCON register. This is a readable and writable register which contains a control bit that allows software to override the WDT Enable Configuration bit, but only if the Configuration bit has disabled the WDT.
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PIC18F66K80 FAMILY 28.3 On-Chip Voltage Regulator FIGURE 28-2: All of the PIC18F66K80 family devices power their core digital logic at a nominal 3.3V. For designs that are required to operate at a higher typical voltage, such as 5V, all family devices incorporate two on-chip regulators that allows the device to run its core logic from VDD.
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PIC18F66K80 FAMILY 28.3.3 OPERATION OF REGULATOR IN SLEEP The difference in the two regulators’ operation arises with Sleep mode. The ultra low-power regulator gives the device the lowest current in the Regulator Enabled mode. The on-chip regulator can go into a lower power mode when the device goes to Sleep by setting the REGSLP bit (WDTCON<7>). This puts the regulator in a standby mode so that the device consumes much less current.
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PIC18F66K80 FAMILY 28.4 In all other power-managed modes, Two-Speed Startup is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO bit is ignored.
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PIC18F66K80 FAMILY 28.5 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. The FSCM function is enabled by setting the FCMEN Configuration bit. When FSCM is enabled, the LF-INTOSC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure.
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PIC18F66K80 FAMILY FIGURE 28-5: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure Device Clock Output CM Output (Q) Failure Detected OSCFIF CM Test Note: 28.5.3 FSCM INTERRUPTS IN POWER-MANAGED MODES By entering a power-managed mode, the clock multiplexer selects the clock source selected by the OSCCON register. Fail-Safe Clock Monitoring of the power-managed clock source resumes in the power-managed mode.
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PIC18F66K80 FAMILY 28.6 Program Verification and Code Protection The user program memory is divided into four blocks. One of these is a boot block of 1 or 2 Kbytes. The remainder of the memory is divided into blocks on binary boundaries. FIGURE 28-6: Each of the blocks has three code protection bits associated with them.
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PIC18F66K80 FAMILY TABLE 28-4: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L — — — — CP3 CP2 CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — 30000Ah CONFIG6L — — — — WRT3 WRT2 WRT1 WRT0 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 30000Ch CONFIG7L — — — — EBTR3 EBTR2 EBTR1 EBTR0 30000Dh CONFIG7H — EBTRB — — — — — — Legend: Shaded cells are unimplemented. 28.6.
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PIC18F66K80 FAMILY FIGURE 28-8: EXTERNAL BLOCK TABLE READ (EBTRx) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh WRT0, EBTR0 = 10 003FFFh 004000h PC = 007FFEh WRT1, EBTR1 = 11 TBLRD* 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRx = 0. The TABLAT register returns a value of ‘0’.
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PIC18F66K80 FAMILY 28.6.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits internal and external writes to data EEPROM. The CPU can always read data EEPROM under normal operation, regardless of the protection bit settings. 28.6.3 CONFIGURATION REGISTER PROTECTION The Configuration registers can be write-protected.
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PIC18F66K80 FAMILY 29.0 INSTRUCTION SET SUMMARY The PIC18F66K80 family of devices incorporates the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 29.
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PIC18F66K80 FAMILY TABLE 29-1: OPCODE FIELD DESCRIPTIONS Field a bbb BSR C, DC, Z, OV, N d dest f fs fd GIE k label mm * *+ *+* n PC PCL PCH PCLATH PCLATU PD PRODH PRODL s TBLPTR TABLAT TO TOS u WDT WREG x zs zd { } [text] (text) [expr]  < >  italics DS39977F-page 484 Description RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register Bit address within an 8-bit file register (0 to 7). Bank Select Register.
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PIC18F66K80 FAMILY FIGURE 29-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 OPCODE Example Instruction 8 7 d 0 a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE 15 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FIL
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PIC18F66K80 FAMILY TABLE 29-2: PIC18F66K80 FAMILY INSTRUCTION SET Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a
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PIC18F66K80 FAMILY TABLE 29-2: PIC18F66K80 FAMILY INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, b, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None
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PIC18F66K80 FAMILY TABLE 29-2: PIC18F66K80 FAMILY INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add Literal and WREG AND Literal with WREG Inclusive OR Literal with WREG Move literal (12-bit) 2nd word 1st word to FSR(f) Move Literal to BSR<3:0> Move Literal to WREG Multiply Literal with WREG Return with Literal in WREG Sub
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PIC18F66K80 FAMILY 29.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (W) + (f)  dest Status Affected: N, OV, C, DC, Z k Operands: 0  k  255 Operation: (W) + k  W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
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PIC18F66K80 FAMILY ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC Syntax: ANDLW Operands: 0  f  255 d [0,1] a [0,1] f {,d {,a}} Operation: (W) + (f) + (C)  dest Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: 00da ffff Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected.
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PIC18F66K80 FAMILY ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0  f  255 d [0,1] a [0,1] f {,d {,a}} Operation: (W) .AND. (f)  dest Status Affected: N, Z Encoding: Description: 0001 Operands: -128  n  127 Operation: if Carry bit is ‘1’, (PC) + 2 + 2n  PC Status Affected: None Encoding: 01da ffff ffff Description: The contents of W are ANDed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W.
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PIC18F66K80 FAMILY BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0  f  255 0b7 a [0,1] f, b {,a} Operation: 0  f Status Affected: None Encoding: 1001 Description: Operands: -128  n  127 Operation: if Negative bit is ‘1’, (PC) + 2 + 2n  PC Status Affected: None Encoding: bbba ffff ffff Description: Bit ‘b’ in register ‘f’ is cleared.
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PIC18F66K80 FAMILY BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN n n Operands: -128  n  127 Operands: -128  n  127 Operation: if Carry bit is ‘0’, (PC) + 2 + 2n  PC Operation: if Negative bit is ‘0’, (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: Description: 1110 0011 nnnn nnnn If the Carry bit is ‘0’, then the program will branch. Encoding: Description: The 2’s complement number, ‘2n’, is added to the PC.
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PIC18F66K80 FAMILY BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ n n Operands: -128  n  127 Operands: -128  n  127 Operation: if Overflow bit is ‘0’, (PC) + 2 + 2n  PC Operation: if Zero bit is ‘0’, (PC) + 2 + 2n  PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0101 nnnn nnnn If the Overflow bit is ‘0’, then the program will branch. Encoding: Description: The 2’s complement number, ‘2n’, is added to the PC.
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PIC18F66K80 FAMILY BRA Unconditional Branch BSF Bit Set f Syntax: BRA Syntax: BSF Operands: 0  f  255 0b7 a [0,1] Operation: 1  f Status Affected: None n Operands: -1024  n  1023 Operation: (PC) + 2 + 2n  PC Status Affected: None Encoding: Description: 1101 1 Cycles: 2 No operation Example: nnnn nnnn Add the 2’s complement number, ‘2n’, to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n.
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PIC18F66K80 FAMILY BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0  f  255 0b7 a [0,1] Operands: 0  f  255 0b<7 a [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: Description: 1011 bbba ffff ffff If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped.
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PIC18F66K80 FAMILY BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV Operands: 0  f  255 0b<7 a [0,1] Operation: (f)  f Status Affected: None Encoding: Description: 0111 Operands: -128  n  127 Operation: if Overflow bit is ‘1’, (PC) + 2 + 2n  PC Status Affected: None Encoding: bbba ffff ffff Description: Bit ‘b’ in data memory location ‘f’ is inverted.
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PIC18F66K80 FAMILY BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} n Operands: -128  n  127 Operands: Operation: if Zero bit is ‘1’, (PC) + 2 + 2n  PC 0  k  1048575 s [0,1] Operation: Status Affected: None (PC) + 4  TOS, k  PC<20:1>; if s = 1 (W)  WS, (STATUS)  STATUSS, (BSR)  BSRS Status Affected: None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ‘1’, then the program will branch.
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PIC18F66K80 FAMILY CLRF Clear f Syntax: CLRF Operands: 0  f  255 a [0,1] f {,a} Operation: 000h  f, 1Z Status Affected: Z Encoding: Description: 0110 101a ffff ffff Clears the contents of the specified register.
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PIC18F66K80 FAMILY COMF Complement f CPFSEQ Syntax: COMF Syntax: CPFSEQ Operands: 0  f  255 a  [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None f {,d {,a}} Operands: 0  f  255 d  [0,1] a  [0,1] Operation: f  dest Status Affected: N, Z Encoding: 0001 Description: 11da ffff ffff The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default).
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PIC18F66K80 FAMILY CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT Syntax: CPFSLT Operands: 0  f  255 a  [0,1] Operands: 0  f  255 a  [0,1] Operation: (f) –W), skip if (f) > (W) (unsigned comparison) Operation: (f) –W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0110 f {,a} 010a ffff ffff Compares the contents of data memory location ‘f’ to the contents of the W by
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PIC18F66K80 FAMILY DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1], then (W<3:0>) + 6  W<3:0>; else (W<3:0>)  W<3:0> 0  f  255 d  [0,1] a  [0,1] Operation: (f) – 1  dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> > 9] or [C = 1], then (W<7:4>) + 6  W<7:4>; C =1 else (W<7:4>)  W<7:4> Status Affected: Description: C Encoding: 0000 0000 0000 DAW adjusts the eight-bi
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PIC18F66K80 FAMILY DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if Not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0  f  255 d  [0,1] a  [0,1] Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (f) – 1  dest, skip if result = 0 Operation: (f) – 1  dest, skip if result  0 Status Affected: None Status Affected: None Encoding: Description: 0010 11da ffff ffff The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W.
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PIC18F66K80 FAMILY GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (f) + 1  dest Status Affected: C, DC, N, OV, Z Operands: 0  k  1048575 Operation: k  PC<20:1> Status Affected: None Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Description: GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range.
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PIC18F66K80 FAMILY INCFSZ Increment f, Skip if 0 INFSNZ Increment f, Skip if Not 0 Syntax: INCFSZ Syntax: INFSNZ 0  f  255 d  [0,1] a  [0,1] f {,d {,a}} f {,d {,a}} Operands: 0  f  255 d  [0,1] a  [0,1] Operands: Operation: (f) + 1  dest, skip if result = 0 Operation: (f) + 1  dest, skip if result  0 Status Affected: None Status Affected: None Encoding: Description: 0011 11da ffff ffff The contents of register ‘f’ are incremented.
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PIC18F66K80 FAMILY IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (W) .OR. (f)  dest Status Affected: N, Z Operands: 0  k  255 Operation: (W) .OR. k  W Status Affected: N, Z Encoding: 0000 1001 kkkk kkkk Description: The contents of W are ORed with the eight-bit literal ‘k’. The result is placed in W.
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PIC18F66K80 FAMILY LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF Operands: 0f2 0  k  4095 Operands: Operation: k  FSRf 0  f  255 d  [0,1] a  [0,1] Status Affected: None Operation: f  dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the file select register pointed to by ‘f’.
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PIC18F66K80 FAMILY MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF fs,fd Syntax: MOVLW k Operands: 0  fs  4095 0  fd  4095 Operands: 0  k  255 Operation: k  BSR Operation: (fs)  fd Status Affected: None Status Affected: None Encoding: 1st word (source) 2nd word (destin.) Encoding: 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’.
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PIC18F66K80 FAMILY MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF Operands: 0  f  255 a  [0,1] Operation: (W)  f Status Affected: None Operands: 0  k  255 Operation: kW Status Affected: None Encoding: 0000 1110 kkkk kkkk The eight-bit literal ‘k’ is loaded into W.
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PIC18F66K80 FAMILY MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW Syntax: MULWF Operands: 0  f  255 a  [0,1] Operation: (W) x (f)  PRODH:PRODL Status Affected: None k Operands: 0  k  255 Operation: (W) x k  PRODH:PRODL Status Affected: None Encoding: Description: 0000 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in the PRODH:PRODL register pair.
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PIC18F66K80 FAMILY NEGF Negate f Syntax: NEGF Operands: 0  f  255 a  [0,1] f {,a} Operation: (f) + 1  f Status Affected: N, OV, C, DC, Z Encoding: Description: 0110 110a ffff If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.
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PIC18F66K80 FAMILY POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS)  bit bucket Operation: (PC + 2)  TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
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PIC18F66K80 FAMILY RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET n Operands: -1024  n  1023 Operands: None Operation: (PC) + 2  TOS, (PC) + 2 + 2n  PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: Description: 1101 Words: 1 Cycles: 2 Q Cycle Activity: Q1 Decode No operation Example: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location.
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PIC18F66K80 FAMILY RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s  [0,1] Operands: 0  k  255 Operation: (TOS)  PC, 1  GIE/GIEH or PEIE/GIEL; if s = 1, (WS)  W, (STATUSS)  STATUS, (BSRS)  BSR, PCLATU, PCLATH are unchanged Operation: k  W, (TOS)  PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: 0000 Description: 0000 0001 1 Cycles: 2 1100 kkkk kkkk Description: W is loaded with the eight-bit l
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PIC18F66K80 FAMILY RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF Operands: s  [0,1] Operands: Operation: (TOS)  PC; if s = 1, (WS)  W, (STATUSS)  STATUS, (BSRS)  BSR, PCLATU, PCLATH are unchanged 0  f  255 d  [0,1] a  [0,1] Operation: (f)  dest, (f<7>)  C, (C)  dest<0> Status Affected: C, N, Z Status Affected: None Encoding: Description: 0000 1 Cycles: 2 No operation Example: 0000 0001 001s Description: Ret
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PIC18F66K80 FAMILY RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF Syntax: RRCF Operands: 0  f  255 d  [0,1] a  [0,1] Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (f)  dest, (f<7>)  dest<0> Operation: Status Affected: N, Z (f)  dest, (f<0>)  C, (C)  dest<7> Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left.
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PIC18F66K80 FAMILY RRNCF Rotate Right f (No Carry) SETF Set f Syntax: RRNCF Syntax: SETF Operands: 0  f  255 d  [0,1] a  [0,1] Operands: 0  f  255 a [0,1] Operation: FFh  f Operation: (f)  dest, (f<0>)  dest<7> Status Affected: None Status Affected: N, Z Encoding: Description: 0100 f {,d {,a}} 00da Encoding: ffff ffff Description: The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
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PIC18F66K80 FAMILY SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h  WDT, 0  WDT postscaler, 1  TO, 0  PD 0 f 255 d  [0,1] a  [0,1] Operation: (W) – (f) – (C) dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Description: Encoding: 0000 0000 0011 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set.
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PIC18F66K80 FAMILY SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF Operands: 0 f 255 d  [0,1] a  [0,1] Operation: (f) – (W) dest Status Affected: N, OV, C, DC, Z Operands: 0 k 255 Operation: k – (W) W Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
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PIC18F66K80 FAMILY SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0  f  255 d  [0,1] a  [0,1] Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (f) – (W) – (C) dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>)  dest<7:4>, (f<7:4>)  dest<3:0> Status Affected: None Encoding: 0101 Description: f {,d {,a}} 10da ffff ffff Subtract W and the Carry flag (borrow) from register ‘f’ (2’s complement method).
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PIC18F66K80 FAMILY TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR))  TABLAT; TBLPTR – No Change if TBLRD *+, (Prog Mem (TBLPTR))  TABLAT; (TBLPTR) + 1  TBLPTR if TBLRD *-, (Prog Mem (TBLPTR))  TABLAT; (TBLPTR) – 1  TBLPTR if TBLRD +*, (TBLPTR) + 1  TBLPTR; (Prog Mem (TBLPTR))  TABLAT Status Affected: None Encoding: Description: 0000 0000 0000 Before Instruction TABLAT TBLPTR MEMORY(
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PIC18F66K80 FAMILY TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Operation: if TBLWT*, (TABLAT)  Holding Register; TBLPTR – No Change if TBLWT*+, (TABLAT)  Holding Register; (TBLPTR) + 1  TBLPTR if TBLWT*-, (TABLAT)  Holding Register; (TBLPTR) – 1  TBLPTR if TBLWT+*, (TBLPTR) + 1  TBLPTR; (TABLAT)  Holding Register Status Affected: Example 2: None Encoding: Description: Before Instruction TABLAT = 55h TBLPTR = 00A35
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PIC18F66K80 FAMILY TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0  f  255 a  [0,1] Operands: 0 k 255 Operation: (W) .XOR. k W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: Description: Encoding: 0110 011a ffff ffff If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction.
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PIC18F66K80 FAMILY XORWF Exclusive OR W with f Syntax: XORWF Operands: 0  f  255 d  [0,1] a  [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 Description: f {,d {,a}} 10da ffff ffff Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
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PIC18F66K80 FAMILY 29.2 A summary of the instructions in the extended instruction set is provided in Table 29-3. Detailed descriptions are provided in Section 29.2.2 “Extended Instruction Set”. The opcode field descriptions in Table 29-1 (page 484) apply to both the standard and extended PIC18 instruction sets.
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PIC18F66K80 FAMILY 29.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return Syntax: Operands: ADDFSR f, k 0  k  63 f  [ 0, 1, 2 ] FSR(f) + k  FSR(f) None 1110 1000 ffkk Syntax: Operands: Operation: ADDULNK k 0  k  63 FSR2 + k  FSR2, (TOS) PC None 1110 1000 11kk Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Example: kkkk The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’.
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PIC18F66K80 FAMILY CALLW Subroutine Call Using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2)  TOS, (W)  PCL, (PCLATH)  PCH, (PCLATU)  PCU 0  zs  127 0  fd  4095 Operation: ((FSR2) + zs)  fd Status Affected: None Status Affected: None Encoding: Description 0000 0000 0001 0100 First, the return address (PC + 2) is pushed onto the return stack.
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PIC18F66K80 FAMILY MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0  zs  127 0  zd  127 Operation: ((FSR2) + zs)  ((FSR2) + zd) Status Affected: None Encoding: 1st word (source) 2nd word (dest.) 1110 1111 Description 1011 xxxx 1zzz xzzz zzzzs zzzzd The contents of the source register are moved to the destination register.
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PIC18F66K80 FAMILY SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return Syntax: Operands: SUBFSR f, k 0  k  63 f  [ 0, 1, 2 ] FSRf – k  FSRf None 1110 1001 Syntax: Operands: Operation: SUBULNK k 0  k  63 FSR2 – k  FSR2, (TOS) PC None 1110 1001 Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode ffkk kkkk The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’.
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PIC18F66K80 FAMILY 29.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing (Section 6.6.1 “Indexed Addressing with Literal Offset”).
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PIC18F66K80 FAMILY ADD W to Indexed (Indexed Literal Offset mode) BSF Syntax: ADDWF Syntax: BSF [k], b Operands: 0  k  95 d  [0,1] Operands: 0  f  95 0b7 Operation: (W) + ((FSR2) + k)  dest Operation: 1  ((FSR2) + k) Status Affected: N, OV, C, DC, Z Status Affected: None ADDWF Encoding: Description: [k] {,d} 0010 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by the value ‘k’. If ‘d’ is ‘0’, the result is stored in W.
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PIC18F66K80 FAMILY 29.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set for the PIC18F66K80 family. This includes the MPLAB C18 C Compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device.
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PIC18F66K80 FAMILY 30.
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PIC18F66K80 FAMILY 30.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 30.
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PIC18F66K80 FAMILY 30.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
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PIC18F66K80 FAMILY 30.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 30.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
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PIC18F66K80 FAMILY 31.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on MCLR with respect to VSS..............................................................................
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PIC18F66K80 FAMILY FIGURE 31-1: VOLTAGE-FREQUENCY GRAPH, REGULATOR ENABLED (INDUSTRIAL/EXTENDED)(1) 6V 5.5V Voltage (VDD) 5V 4V PIC18F66K80 Family 3V 3V 1.8V 0 Note 1: 4 MHz 64 MHz Frequency For VDD values 1.8V to 3V, FMAX = (VDD – 1.72)/0.02 MHz. FIGURE 31-2: VOLTAGE-FREQUENCY GRAPH, REGULATOR DISABLED (INDUSTRIAL/EXTENDED)(1,2) 4V 3.75V 3.6V Voltage (VDD) 3.25V PIC18LF66K80 Family 3V 2.5V 1.
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PIC18F66K80 FAMILY 31.1 DC Characteristics: Supply Voltage PIC18F66K80 Family (Industrial/Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended PIC18F66K80 Family (Industrial, Extended) Param Symbol No. D001 VDD Characteristic Supply Voltage Min Typ Max Units 1.8 1.8 — — 3.6 5.5 V V VDD – 0.3 — VDD + 0.3 V D001C AVDD Analog Supply Voltage D001D AVSS Analog Ground Potential VSS – 0.
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PIC18F66K80 FAMILY 31.2 DC Characteristics: PIC18F66K80 Family (Industrial/Extended) Param No.
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PIC18F66K80 FAMILY 31.2 DC Characteristics: PIC18F66K80 Family (Industrial/Extended) Param No.
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PIC18F66K80 FAMILY 31.2 DC Characteristics: PIC18F66K80 Family (Industrial/Extended) Param No. Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Device Typ Max Units Conditions Supply Current (IDD) Cont.
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PIC18F66K80 FAMILY 31.2 DC Characteristics: PIC18F66K80 Family (Industrial/Extended) Param No. Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Device Typ Max Units Conditions Supply Current (IDD) Cont.
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PIC18F66K80 FAMILY 31.2 DC Characteristics: PIC18F66K80 Family (Industrial/Extended) Param No. Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Device Typ Max Units Conditions Supply Current (IDD) Cont.
PAGE 545
PIC18F66K80 FAMILY 31.2 DC Characteristics: PIC18F66K80 Family (Industrial/Extended) Param No. Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Device Typ Max Units Conditions Supply Current (IDD) Cont.
PAGE 546
PIC18F66K80 FAMILY 31.2 DC Characteristics: PIC18F66K80 Family (Industrial/Extended) Param No. Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Device Typ Max Units Conditions Supply Current (IDD) Cont.
PAGE 547
PIC18F66K80 FAMILY 31.2 DC Characteristics: PIC18F66K80 Family (Industrial/Extended) Param No. Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Device Typ Max Units Conditions Supply Current (IDD) Cont.
PAGE 548
PIC18F66K80 FAMILY 31.2 DC Characteristics: PIC18F66K80 Family (Industrial/Extended) Param No. Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Device Typ Max Units Conditions 270 600 A -40°C 270 600 A +25°C 270 600 A +60°C 300 700 A +85°C Supply Current (IDD) Cont.
PAGE 549
PIC18F66K80 FAMILY 31.2 DC Characteristics: PIC18F66K80 Family (Industrial/Extended) Param No. Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Device Typ Max Units Conditions PIC18LFXXK80 2 5 mA -40°C to +125°C VDD = 3.3V(4) Regulator Disabled PIC18FXXK80 2 5 mA -40°C to +125°C VDD = 3.
PAGE 550
PIC18F66K80 FAMILY 31.2 DC Characteristics: PIC18F66K80 Family (Industrial/Extended) Param No. Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Device Typ Max Units Conditions Supply Current (IDD) Cont.
PAGE 551
PIC18F66K80 FAMILY 31.2 DC Characteristics: PIC18F66K80 Family (Industrial/Extended) Param No. Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Device Typ Max Units Conditions Supply Current (IDD) Cont.
PAGE 552
PIC18F66K80 FAMILY 31.2 DC Characteristics: PIC18F66K80 Family (Industrial/Extended) Param No. Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Device Typ Max Units Conditions Supply Current (IDD) Cont.
PAGE 553
PIC18F66K80 FAMILY 31.2 DC Characteristics: PIC18F66K80 Family (Industrial/Extended) Param No. Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Device Typ Max Units 1.4 4 µA Conditions Supply Current (IDD) Cont.(2,3) PIC18LFXXK80 PIC18LFXXK80 PIC18FXXK80 PIC18FXXK80 Legend: Note 1: 2: 3: 4: 5: -40°C 2.
PAGE 554
PIC18F66K80 FAMILY 31.2 DC Characteristics: PIC18F66K80 Family (Industrial/Extended) Param No. Device Power-Down and Supply Current PIC18F66K80 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Typ Max Units Conditions Module Differential Currents (IWDT, IBOR, IHLVD, IADC) D022 IWDT) D022A IBOR) D022B IHLVD Watchdog Timer PIC18LFXXK80 0.
PAGE 555
PIC18F66K80 FAMILY 31.3 DC Characteristics: PIC18F66K80 Family (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA  +85°C for industrial -40°C TA  +125°C for extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions VSS 0.2 VDD V 1.8V  VDD 5.5V VSS 0.3 VDD V I2C™ enabled SMBus enabled Input Low Voltage All I/O Ports: D031 Schmitt Trigger Buffer D031A RC3 and RC4 VSS 0.8 V D032 MCLR VSS 0.
PAGE 556
PIC18F66K80 FAMILY 31.3 DC Characteristics: PIC18F66K80 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA  +85°C for industrial -40°C TA  +125°C for extended DC CHARACTERISTICS Param Symbol No. VOH D090 Characteristic Min Max Conditions Output High Voltage(1) I/O Ports: D092 Units V PORTA, PORTB, PORTC VDD – 0.7 — V IOH = -3 mA, VDD = 5.5V, -40C to +125C PORTD, PORTE, PORTF, PORTG VDD – 0.
PAGE 557
PIC18F66K80 FAMILY 31.4 DC Characteristics: PIC18F66K80 Family (Industrial) Standard Operating Conditions: 1.8V to 5.5V Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Param No.
PAGE 558
PIC18F66K80 FAMILY TABLE 31-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Param No. Sym Characteristic Min Typ† Max Units VDD + 1.
PAGE 559
PIC18F66K80 FAMILY TABLE 31-2: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V  VDD  5.5V, -40°C  TA  +125°C Param No. Sym Characteristics Min Typ Max Units D300 VIOFF Input Offset Voltage — ±5.
PAGE 560
PIC18F66K80 FAMILY 31.6 31.6.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PAGE 561
PIC18F66K80 FAMILY 31.6.2 TIMING CONDITIONS The temperature and voltages specified in Table 31-5 apply to all timing specifications unless otherwise noted. Figure 31-3 specifies the load conditions for the timing specifications.
PAGE 562
PIC18F66K80 FAMILY 31.6.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 31-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 31-6: Param. No.
PAGE 563
PIC18F66K80 FAMILY TABLE 31-7: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 1.8V TO 5.5V) Sym F10 Characteristic FOSC Oscillator Frequency Range F11 FSYS On-Chip VCO System Frequency Min Typ Max Units 4 — 5 MHz VDD = 1.8-5.5V 4 — 16 MHz VDD = 3.0-5.5V, -40°C to +125°C 16 — 20 MHz VDD = 1.8-5.5V 16 — 64 MHz VDD = 3.0-5.
PAGE 564
PIC18F66K80 FAMILY FIGURE 31-5: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 19 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) New Value Old Value 20, 21 Refer to Figure 31-3 for load conditions. Note: TABLE 31-9: Param No.
PAGE 565
PIC18F66K80 FAMILY TABLE 31-10: CLKO AND I/O TIMING REQUIREMENTS Param. No Symbol Characteristics Min Typ Max Units 150 TadV2alL Address Out Valid to ALE  (address setup time) 0.25 TCY – 10 — — ns 151 TalL2adl ALE  to Address Out Invalid (address hold time) 5 — — ns 155 TalL2oeL ALE to OE  10 0.
PAGE 566
PIC18F66K80 FAMILY FIGURE 31-7: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable 36 TABLE 31-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol No.
PAGE 567
PIC18F66K80 FAMILY FIGURE 31-8: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS For VDIRMAG = 1: VDD VHLVD (HLVDIF set by hardware) (HLVDIF can be cleared in software) VHLVD For VDIRMAG = 0: VDD HLVDIF TABLE 31-12: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA +125°C for extended Param Sym No.
PAGE 568
PIC18F66K80 FAMILY FIGURE 31-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS TxCKI 41 40 42 SOSCO/SCLKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 31-3 for load conditions. TABLE 31-13: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No.
PAGE 569
PIC18F66K80 FAMILY FIGURE 31-10: CAPTURE/COMPARE/PWM TIMINGS (ECCP1, ECCP2 MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 Note: 54 Refer to Figure 31-3 for load conditions. TABLE 31-14: CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP1, ECCP2 MODULES) Param Symbol No. 50 51 TCCL TCCH Characteristic Min Max Units CCPx Input Low No prescaler Time With prescaler 0.5 TCY + 20 — ns 10 — ns CCPx Input High Time 0.
PAGE 570
PIC18F66K80 FAMILY FIGURE 31-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SCK (CKPx = 0) 78 79 79 78 SCK (CKPx = 1) 80 bit 6 - - - - - - 1 MSb SDO LSb 75, 76 SDI MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure 31-3 for load conditions. TABLE 31-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No.
PAGE 571
PIC18F66K80 FAMILY FIGURE 31-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) 81 SCK (CKPx = 0) 79 73 SCK (CKPx = 1) 80 78 MSb SDO bit 6 - - - - - - 1 LSb bit 6 - - - - 1 LSb In 75, 76 SDI MSb In 74 Note: Refer to Figure 31-3 for load conditions. TABLE 31-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No.
PAGE 572
PIC18F66K80 FAMILY FIGURE 31-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKPx = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - - 1 LSb 75, 76 MSb In SDI 77 bit 6 - - - - 1 LSb In 74 73 Refer to Figure 31-3 for load conditions. Note: TABLE 31-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No.
PAGE 573
PIC18F66K80 FAMILY FIGURE 31-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKPx = 0) 70 83 71 72 SCK (CKPx = 1) 80 MSb SDO bit 6 - - - - - - 1 LSb 75, 76 SDI MSb In 77 bit 6 - - - - 1 LSb In 74 Note: Refer to Figure 31-3 for load conditions. TABLE 31-18: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No.
PAGE 574
PIC18F66K80 FAMILY I2C™ BUS START/STOP BITS TIMING FIGURE 31-15: SCL 91 93 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 31-3 for load conditions. TABLE 31-19: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
PAGE 575
PIC18F66K80 FAMILY FIGURE 31-16: I2C™ BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 31-3 for load conditions. TABLE 31-20: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. No.
PAGE 576
PIC18F66K80 FAMILY MSSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS FIGURE 31-17: SCL 93 91 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 31-3 for load conditions. TABLE 31-21: MSSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol No.
PAGE 577
PIC18F66K80 FAMILY TABLE 31-22: MSSP I2C™ BUS DATA REQUIREMENTS Param. Symbol No.
PAGE 578
PIC18F66K80 FAMILY FIGURE 31-19: EUSARTx SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TXx/CKx pin 121 121 RXx/DTx pin 120 Note: 122 Refer to Figure 31-3 for load conditions. TABLE 31-23: EUSART/AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PAGE 579
PIC18F66K80 FAMILY TABLE 31-25: A/D CONVERTER CHARACTERISTICS: PIC18F66K80 FAMILY (INDUSTRIAL/EXTENDED) Param No. Sym Characteristic Min Typ Max Units Conditions VREF  3.0V A01 NR Resolution — — 12 bit A03 EIL Integral Linearity Error — — ±6.0 LSB VDD = 5.0V A04 EDL Differential Linearity Error — ±1 +3.0/-1.0 LSB VDD = 5.0V A06 EOFF Offset Error — ±1 ±9 LSB VDD = 5.0V A07 EGN Gain Error — <±1 ±8.
PAGE 580
PIC18F66K80 FAMILY FIGURE 31-21: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 132 A/D CLK 11 A/D DATA 10 9 ... ... 2 1 0 NEW_DATA OLD_DATA ADRES TCY (Note 1) ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
PAGE 581
PIC18F66K80 FAMILY 32.0 PACKAGING INFORMATION 32.1 Package Marking Information 28-Lead QFN Example XXXXXXXX XXXXXXXX YYWWNNN 18F25K80 /MM e3 1010017 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SPDIP PIC18F26K80/SO e3 1010017 Example PIC18F26K80-I/SP e3 1010017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
PAGE 582
PIC18F66K80 FAMILY 32.
PAGE 583
PIC18F66K80 FAMILY 32.2 Package Details The following sections give the technical details of the packages.
PAGE 584
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PAGE 585
PIC18F66K80 FAMILY /HDG 3ODVWLF 6PDOO 2XWOLQH 62 ± :LGH PP %RG\ >62,&@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E E1 NOTE 1 1 2 3 e b h α A2 A h c φ L A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV β L1 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ ± ± 6WDQGRII $ ± 2YHUDOO :LGWK ( 0ROGHG 3DFNDJH :LG
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PIC18F66K80 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39977F-page 586  2010-2012 Microchip Technology Inc.
PAGE 587
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PIC18F66K80 FAMILY /HDG 3ODVWLF 6KULQN 6PDOO 2XWOLQH 66 ± PP %RG\ >6623@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E E1 1 2 NOTE 1 b e c A2 A φ A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± ± 2YHUDOO :LGWK ( 0RO
PAGE 589
PIC18F66K80 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2012 Microchip Technology Inc.
PAGE 590
PIC18F66K80 FAMILY /HDG 3ODVWLF 'XDO ,Q /LQH 3 ± PLO %RG\ >3',3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV ,1&+(6 0,1 1 120 0$; 3LWFK H 7RS WR 6HDWLQJ 3ODQH $ ± ± 0ROGHG 3DFNDJH 7KLFNQHVV $ ± %DVH WR 6HDWLQJ 3ODQH $ ± ± 6KRXOGHU WR 6KRXOGHU :LGWK ( ±
PAGE 591
PIC18F66K80 FAMILY /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ PP %RG\ >4)1@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 TOP VIEW K L BOTTOM VIEW A A3 A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ 6WDQGRII $ &RQWDFW 7KLFNQHVV $ 2YHUDOO :LGWK (
PAGE 592
PIC18F66K80 FAMILY /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ PP %RG\ >4)1@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS39977F-page 592  2010-2012 Microchip Technology Inc.
PAGE 593
PIC18F66K80 FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A φ c β A2 A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± )RRW /
PAGE 594
PIC18F66K80 FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS39977F-page 594  2010-2012 Microchip Technology Inc.
PAGE 595
PIC18F66K80 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2012 Microchip Technology Inc.
PAGE 596
PIC18F66K80 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39977F-page 596  2010-2012 Microchip Technology Inc.
PAGE 597
PIC18F66K80 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2012 Microchip Technology Inc.
PAGE 598
PIC18F66K80 FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 E e E1 N b NOTE 1 123 NOTE 2 α A φ c A2 β A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± )RRW /HQJ
PAGE 599
PIC18F66K80 FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ  2010-2012 Microchip Technology Inc.
PAGE 600
PIC18F66K80 FAMILY NOTES: DS39977F-page 600  2010-2012 Microchip Technology Inc.
PAGE 601
PIC18F66K80 FAMILY APPENDIX A: REVISION HISTORY Revision A (August 2010) Original data sheet for PIC18F66K80 family devices. Revision B (December 2010) Changes to Section 31.0 “Electrical Characteristics” and minor text edits throughout document. Revision C (January 2011) Section 2.0 “Guidelines for Getting Started with PIC18FXXKXX Microcontrollers” was added to the data sheet. Changes to Section 31.0 “Electrical Characteristics” for PIC18F66K80 family devices. Minor text edits throughout document.
PAGE 602
PIC18F66K80 FAMILY APPENDIX B: MIGRATION TO PIC18F66K80 FAMILY Devices in the PIC18F66K80, PIC18F4580, PIC18F4680 and 18F8680 families are similar in their functions and features. Code can be migrated from the TABLE B-1: other families to the PIC18F66K80 without many changes. The differences between the device families are listed in Table B-1 and Table B-2. For more details on migrating to the PIC18F66K80, refer to “PIC18FXX80 to PIC18FXXK80 Migration Guide” (DS39982).
PAGE 603
PIC18F66K80 FAMILY TABLE B-2: NOTABLE DIFFERENCES BETWEEN 64-PIN DEVICES – PIC18F66K80 AND PIC18F8680 FAMILIES Characteristic Max Operating Frequency PIC18F66K80 Family PIC18F8680 Family 64 MHz 40 MHz Max Program Memory 64K 64K Data Memory (bytes) 3,648 3,328 CTMU Yes No SOSC Oscillator Options Low-power oscillator option for SOSC No options T1CKI Clock T1CKI can be used as a clock without enabling the SOSC oscillator No Up to 16 MHz No Internal Oscillator INTOSC SPI/I2C™ Timers 1
PAGE 604
PIC18F66K80 FAMILY NOTES: DS39977F-page 604  2010-2012 Microchip Technology Inc.
PAGE 605
PIC18F66K80 FAMILY INDEX A A/D .................................................................................... 357 A/D Converter Interrupt, Configuring ........................ 366 Acquisition Requirements ......................................... 367 ADRESH Register..................................................... 364 Analog Port Pins, Configuring................................... 368 Associated Registers ................................................ 371 Automatic Acquisition Time.............
PAGE 606
PIC18F66K80 FAMILY BRG. See Baud Rate Generator. Brown-out Reset (BOR) ...................................................... 82 Detection ..................................................................... 82 Disabling in Sleep Mode ............................................. 82 Software Enabled........................................................ 82 BSF ................................................................................... 495 BTFSC .....................................................
PAGE 607
PIC18F66K80 FAMILY Configuration Mode........................................................... 438 Configuration Register Protection ..................................... 482 Core Features Easy Migration ............................................................ 12 Extended Instruction Set............................................. 11 Memory Options.......................................................... 11 nanoWatt Technology .................................................
PAGE 608
PIC18F66K80 FAMILY Error States....................................................... 452 Form.................................................................. 452 Stuff Bit ............................................................. 452 Error Modes State (diagram) .................................... 453 Error Recognition Mode ............................................ 439 Filter-Mask Truth (table)............................................ 444 Functional Modes.......................................
PAGE 609
PIC18F66K80 FAMILY TBLPTR (Table Pointer) Register ..................... 132 Erase Sequence ....................................................... 134 Erasing...................................................................... 134 Operation During Code-Protect ................................ 137 Reading..................................................................... 133 Table Pointer Boundaries Based on Operation....................... 132 Table Pointer Boundaries ..................................
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PIC18F66K80 FAMILY DAW.......................................................................... 502 DCFSNZ ................................................................... 503 DECF ........................................................................ 502 DECFSZ.................................................................... 503 Extended Instructions ............................................... 525 Considerations when Enabling ......................... 530 Syntax ...............................
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PIC18F66K80 FAMILY RC1/SOSCI .......................................................... 22, 37 RC2/T1G/CCP2.............................................. 22, 28, 37 RC3/REFO/SCL/SCK ..................................... 22, 28, 37 RC4/SDA/SDI ................................................. 22, 28, 37 RC5/SDO........................................................ 22, 28, 37 RC6/CANTX/TX1/CK1/CCP3 ............................... 22, 28 RC6/CCP3...............................................................
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PIC18F66K80 FAMILY TRISC Register ......................................................... 181 PORTD Associated Registers ................................................ 186 LATD Register .......................................................... 184 PORTD Register ....................................................... 184 TRISD Register ......................................................... 184 PORTE Associated Registers ................................................ 188 LATE Register..............
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PIC18F66K80 FAMILY BnDLC (TX/RX Buffer n Data Length Code in Transmit Mode)................................................................ 420 BnDm (TX/RX Buffer n Data Field Byte m in Receive Mode)................................................................ 418 BnDm (TX/RX Buffer n Data Field Byte m in Transmit Mode)................................................................ 418 BnEIDH (TX/RX Buffer n Extended Identifier, High Byte in Receive Mode) ..............................................
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PIC18F66K80 FAMILY SLRCON (Slew Rate Control)................................... 174 SSPCON1 (MSSP Control 1, I2C Mode) .................. 298 SSPCON1 (MSSP Control 1, SPI Mode) .................. 289 SSPCON2 (MSSP Control 2, I2C Master Mode) ...... 299 SSPCON2 (MSSP Control 2, I2C Slave Mode) ........ 300 SSPMSK (I2C Slave Address Mask)......................... 300 SSPSTAT (MSSP Status, I2C Mode)........................ 297 SSPSTAT (MSSP Status, SPI Mode) ....................... 288 STATUS ................
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PIC18F66K80 FAMILY TMR1H Register ....................................................... 209 TMR1L Register........................................................ 209 Timer2 ............................................................................... 221 Associated Registers ................................................ 222 Interrupt..................................................................... 222 Operation .................................................................. 221 Output .......
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PIC18F66K80 FAMILY VDD), Case 1....................................................... 85 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 2....................................................... 85 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise Tpwrt) .................................................. 84 Timer0 and Timer1 External Clock ........................... 568 Timer1 Gate Count Enable Mode ............................. 217 Timer1 Gate Single Pulse Mode .........................
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PIC18F66K80 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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PIC18F66K80 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
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PIC18F66K80 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, such as pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device(1,2) PIC18F25K80, PIC18F26K80, PIC18F45K80, PIC18F46K80, PIC18F65K80, PIC18F66K80 VDD range 1.8V to 5V PIC18F66K80-I/MR 301 = Industrial temp., QFN package, Extended VDD limits, QTP pattern #301. PIC18F66K80-I/PT = Industrial temp.
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PIC18F66K80 FAMILY NOTES: DS39977F-page 620  2010-2012 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.