Datasheet

 2010-2012 Microchip Technology Inc. DS41412F-page 457
PIC18(L)F2X/4XK22
FIGURE 27-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73
74
75, 76
77
78
79
80
79
78
SDI
MSb LSb
bit 6 - - - - - -1
MSb In
bit 6 - - - -1 LSb In
83
Note: Refer to Figure 27-6 for load conditions.
TABLE 27-15: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0 OR 1)
Param.
No.
Symbol Characteristic Min Max Units Conditions
70 TssL2scH,
TssL2scL
SS
 to SCK  or SCK  Input TCY —ns
71 TscH
SCK Input High Time Continuous 25 — ns
72 TscL
SCK Input Low Time Continuous 30 — ns
73 TdiV2scH,
TdiV2scL
Setup Time of SDI Data Input to SCK Edge 25 — ns
74 TscH2diL,
TscL2diL
Hold Time of SDI Data Input to SCK Edge 25 — ns
75 TdoR
SDO Data Output Rise Time — 30 ns
76 TdoF
SDO Data Output Fall Time — 20 ns
77 TssH2doZ SS
 to SDO Output High-Impedance 10 50 ns
80 TscH2doV,
TscL2doV
SDO Data Output Valid after SCK Edge — 60 ns
82 TssL2doV SDO Data Output Valid after SS
 Edge — 60 ns
83 TscH2ssH,
TscL2ssH
SS
 after SCK edge 1.5 TCY + 40 — ns