Datasheet

 2010-2012 Microchip Technology Inc. DS41412F-page 449
PIC18(L)F2X/4XK22
27.11.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 27-7: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
OSC1
CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
1
2
3
3
4
4
TABLE 27-7: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
No.
Symbol Characteristic Min Max Units Conditions
1A F
OSC External CLKIN
Frequency
(1)
DC
DC
DC
0.5
16
64
MHz
MHz
MHz
EC, ECIO Oscillator mode (low power)
EC, ECIO Oscillator mode (medium power)
EC, ECIO Oscillator mode (high power)
Oscillator Frequency
(1)
DC 4 MHz RC Oscillator mode
5 200 kHz LP Oscillator mode
0.1 4 MHz XT Oscillator mode
4 4 MHz HS Oscillator mode, V
DD < 2.7V
4 16 MHz HS Oscillator mode, V
DD 2.7V,
Medium-Power mode (HSMP)
4 20 MHz HS Oscillator mode, V
DD 2.7V,
High-Power mode (HSHP)
1T
OSC External CLKIN Period
(1)
2.0
62.5
15.6
—
—
—
s
ns
ns
EC, ECIO Oscillator mode (low power)
EC, ECIO Oscillator mode (medium power)
EC, ECIO Oscillator mode (high power)
Oscillator Period
(1)
250 — ns RC Oscillator mode
5 200 s LP Oscillator mode
0.25
250
10
250
s
ns
XT Oscillator mode
HS Oscillator mode, V
DD < 2.7V
62.5 250 ns HS Oscillator mode, V
DD 2.7V,
Medium-Power mode (HSMP)
50 250 ns HS Oscillator mode, V
DD 2.7V,
High-Power mode (HSHP)
2T
CY Instruction Cycle Time
(1)
62.5 — ns TCY = 4/FOSC
3T
OSL,
T
OSH
External Clock in (OSC1)
High or Low Time
2.5 — s LP Oscillator mode
30 — ns XT Oscillator mode
10 — ns HS Oscillator mode
4T
OSR,
T
OSF
External Clock in (OSC1)
Rise or Fall Time
— 50 ns LP Oscillator mode
— 20 ns XT Oscillator mode
— 7.5 ns HS Oscillator mode
Note 1: Instruction cycle period (T
CY) equals four times the input oscillator time base period for all configurations except PLL. All
specified values are based on characterization data for that particular oscillator type under standard operating condi-
tions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external
clock applied to the OSC1/CLKIN pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no
clock) for all devices.