Datasheet

PIC18(L)F2X/4XK22
DS41412F-page 340  2010-2012 Microchip Technology Inc.
20.5 Register Definitions: SR Latch Control
REGISTER 20-1: SRCON0: SR LATCH CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SRLEN: SR Latch Enable bit
(1)
1 = SR latch is enabled
0 = SR latch is disabled
bit 6-4 SRCLK<2:0>: SR Latch Clock Divider Bits
000 = Generates a 2 T
OSC wide pulse on DIVSRCLK every 4 peripheral clock cycles
001 = Generates a 2 T
OSC wide pulse on DIVSRCLK every 8 peripheral clock cycles
010 = Generates a 2 T
OSC wide pulse on DIVSRCLK every 16 peripheral clock cycles
011 = Generates a 2 T
OSC wide pulse on DIVSRCLK every 32 peripheral clock cycles
100 = Generates a 2 T
OSC wide pulse on DIVSRCLK every 64 peripheral clock cycles
101 = Generates a 2 T
OSC wide pulse on DIVSRCLK every 128 peripheral clock cycles
110 = Generates a 2 T
OSC wide pulse on DIVSRCLK every 256 peripheral clock cycles
111 = Generates a 2 T
OSC wide pulse on DIVSRCLK every 512 peripheral clock cycles
bit 3 SRQEN: SR Latch Q Output Enable bit
1 = Q is present on the SRQ pin
0 = Q is internal only
bit 2 SRNQEN: SR Latch Q
Output Enable bit
1 =Q is present on the SRNQ pin
0 =Q
is internal only
bit 1 SRPS: Pulse Set Input of the SR Latch bit
(2)
1 = Pulse set input for two TOSC clock cycles
0 = No effect on set input
bit 0 SRPR: Pulse Reset Input of the SR Latch bit
(2)
1 = Pulse reset input for two TOSC clock cycles
0 = No effect on Reset input
Note 1: Changing the SRCLK bits while the SR latch is enabled may cause false triggers to the set and Reset
inputs of the latch.
2: Set only, always reads back ‘0’.