Datasheet

PIC18(L)F2X/4XK22
DS41412F-page 264  2010-2012 Microchip Technology Inc.
bit 0 DHEN: Data Hold Enable bit (I
2
C Slave mode only)
1 = Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the CKP bit
of the SSPxCON1 register and SCLx is held low.
0 = Data holding is disabled
REGISTER 15-4: SSPxCON3: SSPx CONTROL REGISTER 3 (CONTINUED)
Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPxOV is still
set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to
SSPxBUF.
2: This bit has no effect in Slave modes for which Start and Stop condition detection is explicitly listed as
enabled.
3: The ACKTIM Status bit is active only when the AHEN bit or DHEN bit is set.
REGISTER 15-5: SSPxMSK: SSPx MASK REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-1 MSK<7:1>: Mask bits
1 = The received address bit n is compared to SSPxADD<n> to detect I
2
C address match
0 = The received address bit n is not used to detect I
2
C address match
bit 0 MSK<0>: Mask bit for I
2
C Slave mode, 10-bit Address
I
2
C Slave mode, 10-bit address (SSPxM<3:0> = 0111 or 1111):
1 = The received address bit 0 is compared to SSPxADD<0> to detect I
2
C address match
0 = The received address bit 0 is not used to detect I
2
C address match
I
2
C Slave mode, 7-bit address, the bit is ignored