Datasheet

PIC18(L)F2X/4XK22
DS41412F-page 456  2010-2012 Microchip Technology Inc.
FIGURE 27-14: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
TABLE 27-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0 OR 1)
Param.
No.
Symbol Characteristic Min Max Units Conditions
70 TssL2scH,
TssL2scL
SS
 to SCK  or SCK  Input TCY —ns
73 TdiV2scH,
TdiV2scL
Setup Time of SDI Data Input to SCK Edge 25 — ns
74 TscH2diL,
TscL2 diL
Hold Time of SDI Data Input to SCK Edge 25 — ns
75 TdoR
SDO Data Output Rise Time — 30 ns
76 TdoF
SDO Data Output Fall Time — 20 ns
78 TscR
SCK Output Rise Time
(Master mode)
—30ns
79 TscF
SCK Output Fall Time (Master mode) — 20 ns
80 TscH2doV,
TscL2doV
SDO Data Output Valid after SCK Edge — 20 ns
81 TdoV2scH,
TdoV2scL
SDO Data Output Setup to SCK Edge T
CY —ns
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
MSb In
bit 6 - - - - - -1
LSb In
bit 6 - - - -1
LSb
Note: Refer to Figure 27-6 for load conditions.