Datasheet

 2010-2012 Microchip Technology Inc. DS41412F-page 271
PIC18(L)F2X/4XK22
FIGURE 16-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Transmit Shift Reg
Write to TXREGx
BRG Output
(Shift Clock)
TXx/CKx
TXxIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
Word 1
Word 2
Start bit
Stop bit
Start bit
Transmit Shift Reg
Word 1
Word 2
bit 0 bit 1
bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
pin
TABLE 16-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on
Page
BAUDCON1
ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 279
BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 279
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116
IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 128
IPR3
SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 130
PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 124
PIE3
SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 126
PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 119
PIR3
SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 121
PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 55
RCSTA1
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278
SPBRG1 EUSART1 Baud Rate Generator, Low Byte
—
SPBRGH1 EUSART1 Baud Rate Generator, High Byte
—
SPBRG2 EUSART2 Baud Rate Generator, Low Byte
—
SPBRGH2 EUSART2 Baud Rate Generator, High Byte
—
TXREG1 EUSART1 Transmit Register
—
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277
TXREG2 EUSART2 Transmit Register
—
TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous transmission.