Datasheet

 2010-2012 Microchip Technology Inc. DS41412F-page 157
PIC18(L)F2X/4XK22
REGISTER 10-10: LATx: PORTx OUTPUT LATCH REGISTER
(1)
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
LATx7 LATx6 LATx5 LATx4 LATx3 LATx2 LATx1 LATx0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 LATx<7:0>: PORTx Output Latch bit value
(2)
Note 1: Register Description for LATA, LATB, LATC and LATD.
2: Writes to PORTx are written to corresponding LATx register. Reads from PORTx register is return of I/O
pin values.
REGISTER 10-11: LATE: PORTE OUTPUT LATCH REGISTER
(1)
U-0 U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u
— — — — — LATE2 LATE1 LATE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-3 Unimplemented: Read as ‘0’
bit 2-0 LATE<2:0>: PORTE Output Latch bit value
(2)
Note 1: Available on PIC18(L)F4XK22 devices only.
2: Writes to PORTE are written to corresponding LATE register. Reads from PORTE register is return of I/O
pin values.
REGISTER 10-12: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 WPUB<7:0>: Weak Pull-up Register bits
1 = Pull-up enabled on PORT pin
0 = Pull-up disabled on PORT pin