Datasheet

 2010-2012 Microchip Technology Inc. DS41412F-page 131
PIC18(L)F2X/4XK22
REGISTER 9-17: IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — CCP5IP CCP4IP CCP3IP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-3 Unimplemented: Read as ‘0’
bit 2 CCP5IP: CCP5 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 CCP4IP: CCP4 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 CCP3IP: CCP3 Interrupt Priority bit
1 = High priority
0 = Low priority
REGISTER 9-18: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — TMR6IP TMR5IP TMR4IP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-3 Unimplemented: Read as ‘0’
bit 2 TMR6IP: TMR6 to PR6 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR5IP: TMR5 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 TMR4IP: TMR4 to PR4 Match Interrupt Priority bit
1 = High priority
0 = Low priority