Datasheet

PIC18F2XK20/4XK20
DS41303G-page 62  2010 Microchip Technology Inc.
IPR2
PIC18F2XK20 PIC18F4XK20
1111 1111 1111 1111 uuuu uuuu
PIR2
PIC18F2XK20 PIC18F4XK20
0000 0000 0000 0000 uuuu uuuu
(1)
PIE2
PIC18F2XK20 PIC18F4XK20
0000 0000 0000 0000 uuuu uuuu
IPR1
PIC18F2XK20 PIC18F4XK20
1111 1111 1111 1111 uuuu uuuu
PIC18F2XK20
PIC18F4XK20
-111 1111 -111 1111 -uuu uuuu
PIR1
PIC18F2XK20 PIC18F4XK20
0000 0000 0000 0000 uuuu uuuu
(1)
PIC18F2XK20 PIC18F4XK20
-000 0000 -000 0000 -uuu uuuu
(1)
PIE1
PIC18F2XK20 PIC18F4XK20
0000 0000 0000 0000 uuuu uuuu
PIC18F2XK20
PIC18F4XK20
-000 0000 -000 0000 -uuu uuuu
OSCTUNE
PIC18F2XK20 PIC18F4XK20
0000 0000 0000 0000 uuuu uuuu
TRISE
PIC18F2XK20 PIC18F4XK20
---- -111 ---- -111 ---- -uuu
TRISD
PIC18F2XK20 PIC18F4XK20
1111 1111 1111 1111 uuuu uuuu
TRISC
PIC18F2XK20 PIC18F4XK20
1111 1111 1111 1111 uuuu uuuu
TRISB
PIC18F2XK20 PIC18F4XK20
1111 1111 1111 1111 uuuu uuuu
TRISA
(5)
PIC18F2XK20 PIC18F4XK20
1111 1111
(5)
1111 1111
(5)
uuuu uuuu
(5)
LATE
PIC18F2XK20 PIC18F4XK20
---- -xxx ---- -uuu ---- -uuu
LATD
PIC18F2XK20 PIC18F4XK20
xxxx xxxx uuuu uuuu uuuu uuuu
LATC
PIC18F2XK20 PIC18F4XK20
xxxx xxxx uuuu uuuu uuuu uuuu
LATB
PIC18F2XK20 PIC18F4XK20
xxxx xxxx uuuu uuuu uuuu uuuu
LATA
(5)
PIC18F2XK20 PIC18F4XK20
xxxx xxxx
(5)
uuuu uuuu
(5)
uuuu uuuu
(5)
PORTE
PIC18F2XK20 PIC18F4XK20
---- x000 ---- u000 ---- uuuu
PIC18F2XK20
PIC18F4XK20
---- x--- ---- u--- ---- u---
PORTD
PIC18F2XK20 PIC18F4XK20
xxxx xxxx uuuu uuuu uuuu uuuu
PORTC
PIC18F2XK20 PIC18F4XK20
xxxx xxxx uuuu uuuu uuuu uuuu
PORTB
PIC18F2XK20 PIC18F4XK20
xxx0 0000 uuu0 0000 uuuu uuuu
PORTA
(5)
PIC18F2XK20 PIC18F4XK20
xx0x 0000
(5)
uu0u 0000
(5)
uuuu uuuu
(5)
ANSELH
(6)
PIC18F2XK20 PIC18F4XK20
---1 1111 ---1 1111 ---u uuuu
ANSEL
PIC18F2XK20 PIC18F4XK20
1111 1111 1111 1111 uuuu uuuu
IOCB
PIC18F2XK20 PIC18F4XK20
0000 ---- 0000 ---- uuuu ----
WPUB
PIC18F2XK20 PIC18F4XK20
1111 1111 1111 1111 uuuu uuuu
CM1CON0
PIC18F2XK20 PIC18F4XK20
0000 0000 0000 0000 uuuu uuuu
CM2CON0
PIC18F2XK20 PIC18F4XK20
0000 0000 0000 0000 uuuu uuuu
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as
PORTA pins, they are disabled and read ‘0’.
6: All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.